[PATCH 2/2] RTEMS changes for lpc32xx VFP support

[Kirspel, Kevin]

diff --git a/c/src/lib/libbsp/arm/lpc32xx/make/custom/lpc32xx.inc b/c/src/lib/libbsp/arm/lpc32xx/make/custom/lpc32xx.inc
old mode 100644
new mode 100755
index f184741..1d478ce
--- a/c/src/lib/libbsp/arm/lpc32xx/make/custom/lpc32xx.inc
+++ b/c/src/lib/libbsp/arm/lpc32xx/make/custom/lpc32xx.inc
@@ -6,7 +6,8 @@ include $(RTEMS_ROOT)/make/custom/default.cfg
 RTEMS_CPU = arm
-CPU_CFLAGS = -mcpu=arm926ej-s -mthumb
+#CPU_CFLAGS = -mcpu=arm926ej-s -mthumb
+CPU_CFLAGS = -mcpu=arm926ej-s -mfpu=vfp -mfloat-abi=softfp
 CFLAGS_OPTIMIZE_V ?= -O2 -g
CFLAGS_OPTIMIZE_V += -ffunction-sections -fdata-sections
diff --git a/c/src/lib/libbsp/arm/shared/start/start.S b/c/src/lib/libbsp/arm/shared/start/start.S
old mode 100644
new mode 100755
index 30501be..cb3bff7
--- a/c/src/lib/libbsp/arm/shared/start/start.S
+++ b/c/src/lib/libbsp/arm/shared/start/start.S
@@ -19,9 +19,9 @@
  */
 #include <rtems/asm.h>
-#include <rtems/system.h>
+#include <rtems/system.h>
#include <rtems/score/cpu.h>
-
+
#include <bspopts.h>
#include <bsp/irq.h>
#include <bsp/linker-symbols.h>
@@ -265,6 +265,7 @@ bsp_start_skip_hyp_svc_switch:
               /* Stay in SVC mode */
 #ifdef ARM_MULTILIB_VFP
+#ifndef ARM_MULTILIB_ARCH_V5TEJ
               /* Read CPACR */
               mrc p15, 0, r0, c1, c0, 2
@@ -280,11 +281,18 @@ bsp_start_skip_hyp_svc_switch:
               /* Write CPACR */
               mcr p15, 0, r0, c1, c0, 2
               isb
+#endif
                /* Enable FPU */
               mov r0, #(1 << 30)
               vmsr FPEXC, r0
+#ifdef ARM_MULTILIB_ARCH_V5TEJ
+             /* Enable FPU Run Fast*/
+             mov r0, #(3 << 24)
+             vmsr FPSCR, r0
+#endif
+
#ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION
               bl bsp_start_init_registers_vfp
#endif
@@ -399,6 +407,7 @@ _start:
#endif
 #ifdef ARM_MULTILIB_VFP
+#ifndef ARM_MULTILIB_ARCH_V5TEJ
               /*
                * Enable CP10 and CP11 coprocessors for privileged and user mode in
                * CPACR (bits 20-23).  Ensure that write to register completes.
@@ -409,6 +418,7 @@ _start:
               str           r1, [r0]
               dsb
               isb
+#endif
 #ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION
               bl bsp_start_init_registers_vfp
diff --git a/cpukit/score/cpu/arm/arm-context-validate.S b/cpukit/score/cpu/arm/arm-context-validate.S
old mode 100644
new mode 100755
index fdfb6c1..6485993
--- a/cpukit/score/cpu/arm/arm-context-validate.S
+++ b/cpukit/score/cpu/arm/arm-context-validate.S
@@ -46,7 +46,11 @@
                .section .text
+#ifdef __thumb__
FUNCTION_THUMB_ENTRY(_CPU_Context_validate)
+#else
+FUNCTION_ENTRY(_CPU_Context_validate)
+#endif
                /* Save */
@@ -99,12 +103,16 @@ FUNCTION_THUMB_ENTRY(_CPU_Context_validate)
#ifdef ARM_MULTILIB_VFP
               /* R3 contains the FPSCR */
               vmrs      r3, FPSCR
+#ifdef ARM_MULTILIB_ARCH_V5TEJ
+             ldr          r4, =0xf000001f
+#else
               movs     r4, #0x001f
#ifdef ARM_MULTILIB_ARCH_V7M
               movt     r4, #0xf000
#else
               movt     r4, #0xf800
#endif
+#endif
               bic          r3, r3, r4
               and        r4, r4, r0
               orr          r3, r3, r4
diff --git a/cpukit/score/cpu/arm/arm-context-volatile-clobber.S b/cpukit/score/cpu/arm/arm-context-volatile-clobber.S
old mode 100644
new mode 100755
index 7970b8e..cf3f428
--- a/cpukit/score/cpu/arm/arm-context-volatile-clobber.S
+++ b/cpukit/score/cpu/arm/arm-context-volatile-clobber.S
@@ -20,7 +20,11 @@
                .section .text
+#ifdef __thumb__
FUNCTION_THUMB_ENTRY(_CPU_Context_volatile_clobber)
+#else
+FUNCTION_ENTRY(_CPU_Context_volatile_clobber)
+#endif
 .macro clobber_register reg
               sub         r0, r0, #1
@@ -29,8 +33,12 @@ FUNCTION_THUMB_ENTRY(_CPU_Context_volatile_clobber)
 #ifdef ARM_MULTILIB_VFP
               vmrs      r1, FPSCR
+#ifdef ARM_MULTILIB_ARCH_V5TEJ
+             ldr          r2, =0xf800001f
+#else
               movs     r2, #0x001f
               movt     r2, #0xf800
+#endif
               bic          r1, r1, r2
               and        r2, r2, r0
               orr          r1, r1, r2
diff --git a/cpukit/score/cpu/arm/rtems/score/arm.h b/cpukit/score/cpu/arm/rtems/score/arm.h
old mode 100644
new mode 100755
index 666ee54..929585e
--- a/cpukit/score/cpu/arm/rtems/score/arm.h
+++ b/cpukit/score/cpu/arm/rtems/score/arm.h
@@ -35,6 +35,10 @@ extern "C" {
#elif defined(__ARM_ARCH_6M__)
   #define CPU_MODEL_NAME "ARMv6M"
   #define ARM_MULTILIB_ARCH_V6M
+#elif defined(__ARM_ARCH_5TEJ__)
+  #define CPU_MODEL_NAME "ARMv5TEJ"
+  #define ARM_MULTILIB_ARCH_V5TEJ
+  #define ARM_MULTILIB_ARCH_V4
#else
   #define CPU_MODEL_NAME "ARMv4"
   #define ARM_MULTILIB_ARCH_V4
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