[PATCH 3/6] Improve OR1k context handling
jakob.viketoft at gmail.com
jakob.viketoft at gmail.com
Sat Feb 20 08:33:33 UTC 2016
From: Jakob Viketoft <jakob.viketoft at aacmicrotec.com>
---
cpukit/score/cpu/or1k/or1k-context-initialize.c | 13 ++-
cpukit/score/cpu/or1k/or1k-context-switch.S | 113 ++++++++++++-----------
2 files changed, 69 insertions(+), 57 deletions(-)
diff --git a/cpukit/score/cpu/or1k/or1k-context-initialize.c b/cpukit/score/cpu/or1k/or1k-context-initialize.c
index a7205e3..d37458e 100644
--- a/cpukit/score/cpu/or1k/or1k-context-initialize.c
+++ b/cpukit/score/cpu/or1k/or1k-context-initialize.c
@@ -29,13 +29,22 @@ void _CPU_Context_Initialize(
void *tls_area
)
{
- /* Decrement 200 byte to account for red-zone */
- uint32_t stack = ((uint32_t) stack_area_begin) - 200;
+ /* Decrement to account for redzone */
+ uint32_t stack = ((uint32_t) stack_area_begin) - REDZONE_SIZE;
uint32_t sr;
uint32_t stack_high = stack + stack_area_size;
sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
+ /* Make sure we will adhere to the requested level */
+ if (new_level > 0) {
+ /* Interrupts disable in our local sr */
+ sr &= ~(CPU_OR1K_SPR_SR_IEE | CPU_OR1K_SPR_SR_TEE);
+ } else {
+ /* Interrupts enable in our local sr */
+ sr |= CPU_OR1K_SPR_SR_IEE | CPU_OR1K_SPR_SR_TEE;
+ }
+
memset(context, 0, sizeof(*context));
context->r1 = stack_high;
diff --git a/cpukit/score/cpu/or1k/or1k-context-switch.S b/cpukit/score/cpu/or1k/or1k-context-switch.S
index 91521e4..2a98cac 100644
--- a/cpukit/score/cpu/or1k/or1k-context-switch.S
+++ b/cpukit/score/cpu/or1k/or1k-context-switch.S
@@ -22,93 +22,96 @@ PUBLIC(_CPU_Context_restore_fp)
PUBLIC(_CPU_Context_save_fp)
SYM(_CPU_Context_switch):
- l.sw 0(r3),r1
- l.sw 4(r3),r2
- l.sw 8(r3),r3
- l.sw 12(r3),r4
- l.sw 16(r3),r5
- l.sw 20(r3),r6
- l.sw 24(r3),r7
- l.sw 28(r3),r8
- l.sw 32(r3),r9
- /* Skip r10 as it's preserved to be used by TLS */
- /* The following set if registers are preserved across function calls */
- l.sw 52(r3),r14
- l.sw 60(r3),r16
- l.sw 68(r3),r18
- l.sw 76(r3),r20
- l.sw 84(r3),r22
- l.sw 92(r3),r24
- l.sw 100(r3),r26
- l.sw 108(r3),r28
- l.sw 116(r3),r30
+ l.sw OR1K_CC_GPR1(r3), r1
+ l.sw OR1K_CC_GPR2(r3), r2
+ l.sw OR1K_CC_GPR3(r3), r3
+ l.sw OR1K_CC_GPR4(r3), r4
+ l.sw OR1K_CC_GPR5(r3), r5
+ l.sw OR1K_CC_GPR6(r3), r6
+ l.sw OR1K_CC_GPR7(r3), r7
+ l.sw OR1K_CC_GPR8(r3), r8
+ l.sw OR1K_CC_GPR9(r3), r9
+ /* The following set of registers are preserved across function calls
+ * (callee-saved) */
+ l.sw OR1K_CC_GPR10(r3), r10
+ l.sw OR1K_CC_GPR12(r3), r12
+ l.sw OR1K_CC_GPR14(r3), r14
+ l.sw OR1K_CC_GPR16(r3), r16
+ l.sw OR1K_CC_GPR18(r3), r18
+ l.sw OR1K_CC_GPR20(r3), r20
+ l.sw OR1K_CC_GPR22(r3), r22
+ l.sw OR1K_CC_GPR24(r3), r24
+ l.sw OR1K_CC_GPR26(r3), r26
+ l.sw OR1K_CC_GPR28(r3), r28
+ l.sw OR1K_CC_GPR30(r3), r30
/* Supervision Register */
- l.mfspr r13,r0, CPU_OR1K_SPR_SR
- l.sw 124(r3),r13
+ l.mfspr r13, r0, CPU_OR1K_SPR_SR
+ l.sw OR1K_CC_SR(r3), r13
/* EPCR */
l.mfspr r13, r0, CPU_OR1K_SPR_EPCR0
- l.sw 128(r3), r13 /* epcr */
+ l.sw OR1K_CC_EPCR0(r3), r13
/* EEAR */
l.mfspr r13, r0, CPU_OR1K_SPR_EEAR0
- l.sw 132(r3), r13 /* eear */
+ l.sw OR1K_CC_EEAR0(r3), r13
/* ESR */
l.mfspr r13, r0, CPU_OR1K_SPR_ESR0
- l.sw 136(r3), r13 /* esr */
+ l.sw OR1K_CC_ESR0(r3), r13
SYM(restore):
- l.lwz r13,124(r4)
- l.mtspr r0,r13, CPU_OR1K_SPR_SR
-
- /* Exception level related registers */
+ l.lwz r13, OR1K_CC_SR(r4)
+ l.mtspr r0, r13, CPU_OR1K_SPR_SR
/* EPCR */
- l.lwz r13, 128(r4)
+ l.lwz r13, OR1K_CC_EPCR0(r4)
l.mtspr r0, r13, CPU_OR1K_SPR_EPCR0
/* EEAR */
- l.lwz r13, 132(r4)
+ l.lwz r13, OR1K_CC_EEAR0(r4)
l.mtspr r0, r13, CPU_OR1K_SPR_EEAR0
/* ESR */
- l.lwz r13, 136(r4)
+ l.lwz r13, OR1K_CC_ESR0(r4)
l.mtspr r0, r13, CPU_OR1K_SPR_ESR0
- l.lwz r1,0(r4)
- l.lwz r2,4(r4)
- l.lwz r3,8(r4)
+ l.lwz r1, OR1K_CC_GPR1(r4)
+ l.lwz r2, OR1K_CC_GPR2(r4)
+ l.lwz r3, OR1K_CC_GPR3(r4)
/* Skip r4 as it contains the current buffer address */
- l.lwz r5,16(r4)
- l.lwz r6,20(r4)
- l.lwz r7,24(r4)
- l.lwz r8,28(r4)
- l.lwz r9,32(r4)
- l.lwz r14,52(r4)
- l.lwz r16,60(r4)
- l.lwz r18,68(r4)
- l.lwz r20,76(r4)
- l.lwz r22,84(r4)
- l.lwz r24,92(r4)
- l.lwz r26,100(r4)
- l.lwz r28,108(r4)
- l.lwz r30,116(r4)
-
- l.lwz r4,12(r4)
-
- l.jr r9
+ l.lwz r5, OR1K_CC_GPR5(r4)
+ l.lwz r6, OR1K_CC_GPR6(r4)
+ l.lwz r7, OR1K_CC_GPR7(r4)
+ l.lwz r8, OR1K_CC_GPR8(r4)
+ l.lwz r9, OR1K_CC_GPR9(r4)
+ l.lwz r10, OR1K_CC_GPR10(r4)
+ l.lwz r12, OR1K_CC_GPR12(r4)
+ l.lwz r14, OR1K_CC_GPR14(r4)
+ l.lwz r16, OR1K_CC_GPR16(r4)
+ l.lwz r18, OR1K_CC_GPR18(r4)
+ l.lwz r20, OR1K_CC_GPR20(r4)
+ l.lwz r22, OR1K_CC_GPR22(r4)
+ l.lwz r24, OR1K_CC_GPR24(r4)
+ l.lwz r26, OR1K_CC_GPR26(r4)
+ l.lwz r28, OR1K_CC_GPR28(r4)
+ l.lwz r30, OR1K_CC_GPR30(r4)
+
+ l.lwz r4, OR1K_CC_GPR4(r4)
+
+ l.jr r9
l.nop
SYM(_CPU_Context_restore):
- l.add r4,r3,r0
- l.add r13,r0,r0
+ l.add r4, r3, r0
l.j restore
l.nop
SYM(_CPU_Context_restore_fp):
+ l.jr r9
l.nop
SYM(_CPU_Context_save_fp):
+ l.jr r9
l.nop
--
1.7.10.4
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