[PATCH 2/6] OR1k exception handling and start code
jakob.viketoft at gmail.com
jakob.viketoft at gmail.com
Sat Feb 20 08:33:07 UTC 2016
From: Jakob Viketoft <jakob.viketoft at aacmicrotec.com>
- Correct start vector table.
- Add proper init of registers and caches
- Add more information on unhandled exceptions
- Use defines instead of hardcoded values for readability
---
c/src/lib/libbsp/or1k/generic_or1k/start/start.S | 258 +++++++++++++++++---
cpukit/score/cpu/or1k/or1k-exception-default.c | 1 +
cpukit/score/cpu/or1k/or1k-exception-frame-print.c | 11 +-
cpukit/score/cpu/or1k/or1k-exception-handler-low.S | 220 ++++++++---------
4 files changed, 343 insertions(+), 147 deletions(-)
diff --git a/c/src/lib/libbsp/or1k/generic_or1k/start/start.S b/c/src/lib/libbsp/or1k/generic_or1k/start/start.S
index 26991c8..7a182df 100644
--- a/c/src/lib/libbsp/or1k/generic_or1k/start/start.S
+++ b/c/src/lib/libbsp/or1k/generic_or1k/start/start.S
@@ -1,11 +1,16 @@
/*
* Copyright (c) 2014-2015 Hesham ALMatary <heshamelmatary at gmail.com>
+ * Copyright (c) 2014-2016 ÅAC Microtec AB <www.aacmicrotec.com>
+ * Jakob Viketoft <jakob.viketoft at aacmicrotec.com>
*
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE
*/
#include <bsp/linker-symbols.h>
+#include <rtems/score/or1k-utility.h>
+
+ .extern _ISR_Handler
/* The following macro defines the first instructions every exception
* should execute before jumping to its handler function from the
@@ -16,34 +21,22 @@
*/
#define EXCEPTION_SETUP(vector) \
l.nop ;\
- l.addi r1, r1, -200 ;\
- l.sw 0(r1), r3; \
+ /* Add space for redzone and make space on the current stack \
+ * (from the interrupted thread) */ \
+ l.addi r1, r1, -(REDZONE_SIZE + EX_FRAME_SIZE); \
+ l.sw OR1K_EC_GPR3(r1), r3; \
l.addi r3, r0, vector; \
l.j _ISR_Handler; \
l.nop
.extern boot_card
- .extern bsp_section_bss_begin
- .extern bsp_section_bss_end
-
- .extern bsp_start_vector_table_end
- .extern bsp_start_vector_table_size
- .extern bsp_vector_table_size
- .extern bsp_section_stack_begin
-
- .extern exception_frame_save
- .extern _OR1K_Exception_Process
.extern _OR1K_Exception_default
- .extern rtems_clock_tick
- .extern _exit
- .extern printk
- .extern bsp_interrupt_handler_default
/* Global symbols */
.global _start
.global bsp_start_vector_table_begin
-/* Popualte HW vector table */
+/* Populate HW vector table */
.section .vector, "ax"
@@ -61,7 +54,7 @@ _dPageFault:
EXCEPTION_SETUP(3)
.org 0x400
-_iPageFaule:
+_iPageFault:
EXCEPTION_SETUP(4)
.org 0x500
@@ -105,18 +98,74 @@ _trap:
EXCEPTION_SETUP(14)
.org 0xF00
-_undef1:
+_res_future1:
EXCEPTION_SETUP(15)
-.org 0x1500
-_undef2:
+.org 0x1000
+_res_future2:
EXCEPTION_SETUP(16)
-.org 0x1900
-_undef3:
+.org 0x1100
+_res_future3:
EXCEPTION_SETUP(17)
+.org 0x1200
+_res_future4:
+ EXCEPTION_SETUP(18)
+
+.org 0x1300
+_res_future5:
+ EXCEPTION_SETUP(19)
+
+.org 0x1400
+_res_future6:
+ EXCEPTION_SETUP(20)
+
+.org 0x1500
+_res_impspec1:
+ EXCEPTION_SETUP(21)
+
+.org 0x1600
+_res_impspec2:
+ EXCEPTION_SETUP(22)
+
+.org 0x1700
+_res_impspec3:
+ EXCEPTION_SETUP(23)
+
+.org 0x1800
+_res_impspec4:
+ EXCEPTION_SETUP(24)
+
+.org 0x1900
+_res_custom1:
+ EXCEPTION_SETUP(25)
+
+.org 0x1A00
+_res_custom2:
+ EXCEPTION_SETUP(26)
+
+.org 0x1B00
+_res_custom3:
+ EXCEPTION_SETUP(27)
+
+.org 0x1C00
+_res_custom4:
+ EXCEPTION_SETUP(28)
+
+.org 0x1D00
+_res_custom5:
+ EXCEPTION_SETUP(29)
+
+.org 0x1E00
+_res_custom6:
+ EXCEPTION_SETUP(30)
+
.org 0x1F00
+_res_custom7:
+ EXCEPTION_SETUP(31)
+
+.org 0x2000
bsp_start_vector_table_begin:
@@ -127,7 +176,7 @@ bsp_start_vector_table_begin:
.word _OR1K_Exception_default /* Instruction Page Fault */
.word _OR1K_Exception_default /* Tick timer */
.word _OR1K_Exception_default /* Alignment */
- .word _OR1K_Exception_default /* Undefiend Instruction */
+ .word _OR1K_Exception_default /* Undefined Instruction */
.word _OR1K_Exception_default /* External Interrupt */
.word _OR1K_Exception_default /* Data TLB Miss */
.word _OR1K_Exception_default /* Instruction TLB Miss */
@@ -135,8 +184,22 @@ bsp_start_vector_table_begin:
.word _OR1K_Exception_default /* System Call */
.word _OR1K_Exception_default /* Floating Point Exception */
.word _OR1K_Exception_default /* Trap */
- .word _OR1K_Exception_default /* Reserver for future use */
+ .word _OR1K_Exception_default /* Reserved for future use */
+ .word _OR1K_Exception_default /* Reserved for future use */
+ .word _OR1K_Exception_default /* Reserved for future use */
+ .word _OR1K_Exception_default /* Reserved for future use */
+ .word _OR1K_Exception_default /* Reserved for future use */
+ .word _OR1K_Exception_default /* Reserved for future use */
+ .word _OR1K_Exception_default /* Reserved for implementation-specific */
.word _OR1K_Exception_default /* Reserved for implementation-specific */
+ .word _OR1K_Exception_default /* Reserved for implementation-specific */
+ .word _OR1K_Exception_default /* Reserved for implementation-specific */
+ .word _OR1K_Exception_default /* Reserved for custom exceptions. */
+ .word _OR1K_Exception_default /* Reserved for custom exceptions. */
+ .word _OR1K_Exception_default /* Reserved for custom exceptions. */
+ .word _OR1K_Exception_default /* Reserved for custom exceptions. */
+ .word _OR1K_Exception_default /* Reserved for custom exceptions. */
+ .word _OR1K_Exception_default /* Reserved for custom exceptions. */
.word _OR1K_Exception_default /* Reserved for custom exceptions. */
bsp_start_vector_table_end:
@@ -145,10 +208,145 @@ bsp_start_vector_table_end:
.type _start, at function
_start:
+ /* Clear r0 */
+ l.movhi r0, 0
+
/* Set SR register to Supervision mode */
- l.ori r1, r0, 0x1
- l.mtspr r0, r1, 17
+ l.ori r1, r0, CPU_OR1K_SPR_SR_SM
+ l.mtspr r0, r1, CPU_OR1K_SPR_SR
+
+ /* Clear all registers */
+ l.movhi r1, 0
+ l.movhi r2, 0
+ l.movhi r3, 0
+ l.movhi r4, 0
+ l.movhi r5, 0
+ l.movhi r6, 0
+ l.movhi r7, 0
+ l.movhi r8, 0
+ l.movhi r9, 0
+ l.movhi r10, 0
+ l.movhi r11, 0
+ l.movhi r12, 0
+ l.movhi r13, 0
+ l.movhi r14, 0
+ l.movhi r15, 0
+ l.movhi r16, 0
+ l.movhi r17, 0
+ l.movhi r18, 0
+ l.movhi r19, 0
+ l.movhi r20, 0
+ l.movhi r21, 0
+ l.movhi r22, 0
+ l.movhi r23, 0
+ l.movhi r24, 0
+ l.movhi r25, 0
+ l.movhi r26, 0
+ l.movhi r27, 0
+ l.movhi r28, 0
+ l.movhi r29, 0
+ l.movhi r30, 0
+ l.movhi r31, 0
+
+ /* Disable all interrupts */
+ l.mtspr r0, r0, CPU_OR1K_SPR_PICMR
+
+ /* Clear all pending interrupts */
+ l.mtspr r0, r0, CPU_OR1K_SPR_PICSR
+
+ /* Disable Tick-Timer */
+ l.mtspr r0, r0, CPU_OR1K_SPR_TTMR
+ /* Zero the counter */
+ l.mtspr r0, r0, CPU_OR1K_SPR_TTCR
+
+ /* Check if IC present and skip otherwise */
+ l.mfspr r24, r0, CPU_OR1K_SPR_UPR
+ l.andi r26, r24, CPU_OR1K_SPR_UPR_ICP
+ l.sfeq r26, r0
+ l.bf 9f
+ l.nop
+
+ /* Disable I-Cache */
+ l.mfspr r13, r0, CPU_OR1K_SPR_SR
+ l.addi r11, r0, -1
+ l.xori r11, r11, CPU_OR1K_SPR_SR_ICE
+ l.and r11, r13, r11
+ l.mtspr r0, r11, CPU_OR1K_SPR_SR
+
+ /* Establish cache block size
+ If BS=0, 16;
+ If BS=1, 32;
+ r14 contain block size
+ */
+ l.mfspr r24, r0, CPU_OR1K_SPR_ICCFGR
+ l.andi r26, r24, CPU_OR1K_SPR_ICCFGR_CBS
+ l.srli r28, r26, 7
+ l.ori r30, r0, 16
+ l.sll r14, r30, r28
+
+ /* Establish number of cache sets
+ r16 contains number of cache sets
+ r28 contains log(# of cache sets)
+ */
+ l.andi r26, r24, CPU_OR1K_SPR_ICCFGR_NCS
+ l.srli r28, r26, 3
+ l.ori r30, r0, 1
+ l.sll r16, r30, r28
+
+ /* Invalidate IC */
+ l.addi r6, r0, 0
+ l.sll r5, r14, r28
+1:
+ l.mtspr r0, r6, CPU_OR1K_SPR_ICBIR
+ l.sfne r6, r5
+ l.bf 1b
+ l.add r6, r6, r14
+
+9:
+ /* Check if DC present and skip otherwise */
+ l.mfspr r24, r0, CPU_OR1K_SPR_UPR
+ l.andi r26, r24, CPU_OR1K_SPR_UPR_DCP
+ l.sfeq r26, r0
+ l.bf 9f
+ l.nop
+ /* Disable DC */
+ l.mfspr r6, r0, CPU_OR1K_SPR_SR
+ l.addi r5, r0, -1
+ l.xori r5, r5, CPU_OR1K_SPR_SR_DCE
+ l.and r5, r6, r5
+ l.mtspr r0, r5, CPU_OR1K_SPR_SR
+
+ /* Establish cache block size
+ If BS=0, 16;
+ If BS=1, 32;
+ r14 contain block size
+ */
+ l.mfspr r24, r0,CPU_OR1K_SPR_DCCFGR
+ l.andi r26, r24, CPU_OR1K_SPR_DCCFGR_CBS
+ l.srli r28, r26, 7
+ l.ori r30, r0, 16
+ l.sll r14, r30, r28
+
+ /* Establish number of cache sets
+ r16 contains number of cache sets
+ r28 contains log(# of cache sets)
+ */
+ l.andi r26, r24, CPU_OR1K_SPR_DCCFGR_NCS
+ l.srli r28, r26, 3
+ l.ori r30, r0, 1
+ l.sll r16, r30, r28
+
+ /* Invalidate DC */
+ l.addi r6, r0, 0
+ l.sll r5, r14, r28
+1:
+ l.mtspr r0, r6, CPU_OR1K_SPR_DCBIR
+ l.sfne r6, r5
+ l.bf 1b
+ l.add r6, r6, r14
+
+9:
/* load stack and frame pointers */
l.movhi r1, hi(bsp_section_stack_begin)
l.ori r1, r1, lo(bsp_section_stack_begin)
diff --git a/cpukit/score/cpu/or1k/or1k-exception-default.c b/cpukit/score/cpu/or1k/or1k-exception-default.c
index 037a169..a7b309a 100644
--- a/cpukit/score/cpu/or1k/or1k-exception-default.c
+++ b/cpukit/score/cpu/or1k/or1k-exception-default.c
@@ -18,5 +18,6 @@ void _OR1K_Exception_default(uint32_t vector, CPU_Exception_frame *frame);
void _OR1K_Exception_default(uint32_t vector, CPU_Exception_frame *frame)
{
+ printk("Unhandled exception %u\n", vector);
rtems_fatal( RTEMS_FATAL_SOURCE_EXCEPTION, (rtems_fatal_code) frame );
}
diff --git a/cpukit/score/cpu/or1k/or1k-exception-frame-print.c b/cpukit/score/cpu/or1k/or1k-exception-frame-print.c
index 75e169c..0745089 100644
--- a/cpukit/score/cpu/or1k/or1k-exception-frame-print.c
+++ b/cpukit/score/cpu/or1k/or1k-exception-frame-print.c
@@ -16,7 +16,14 @@
void _CPU_Exception_frame_print( const CPU_Exception_frame *frame )
{
uint32_t i;
- for ( i = 0; i < 32; ++i ) {
- printk( "r%02i = 0x%016x\n",i, frame->r[i]);
+
+ /* r0 is a special case (always zero) */
+ printk( "r%02i = 0x%016x\n", 0, 0);
+ for ( i = 1; i < 32; ++i ) {
+ printk( "r%02i = 0x%016x\n", i, frame->r[i]);
}
+
+ printk( "EPCR = 0x%016x\n", frame->epcr);
+ printk( "EEAR = 0x%016x\n", frame->eear);
+ printk( "ESR = 0x%016x\n", frame->esr);
}
diff --git a/cpukit/score/cpu/or1k/or1k-exception-handler-low.S b/cpukit/score/cpu/or1k/or1k-exception-handler-low.S
index 96d0c8e..5f61b00 100644
--- a/cpukit/score/cpu/or1k/or1k-exception-handler-low.S
+++ b/cpukit/score/cpu/or1k/or1k-exception-handler-low.S
@@ -13,6 +13,9 @@
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*
+ * Contributor(s):
+ * COPYRIGHT (c) 2016 ÅAC Microtec AB
+ * Jakob Viketoft <jakob.viketoft at aacmicrotec.com>
*/
#ifdef HAVE_CONFIG_H
@@ -21,7 +24,7 @@
#include <rtems/asm.h>
#include <rtems/score/percpu.h>
-#include "rtems/score/or1k-utility.h"
+#include <rtems/score/or1k-utility.h>
.align 4
.text
@@ -30,96 +33,88 @@ PUBLIC(_ISR_Handler)
SYM(_ISR_Handler):
- l.addi r1, r1, -140
-
- l.sw 8(r1),r2
- /* r3 is saved by BSP exception handler */
- l.sw 16(r1),r4
- l.sw 20(r1),r5
- l.sw 24(r1),r6
- l.sw 28(r1),r7
- l.sw 32(r1),r8
- l.sw 36(r1),r9
- l.sw 40(r1),r10
- l.sw 44(r1),r11
- l.sw 48(r1),r12
- l.sw 52(r1),r13
- l.sw 56(r1),r14
- l.sw 60(r1),r15
- l.sw 64(r1),r16
- l.sw 68(r1),r17
- l.sw 72(r1),r18
- l.sw 76(r1),r19
- l.sw 80(r1),r20
- l.sw 84(r1),r21
- l.sw 88(r1),r22
- l.sw 92(r1),r23
- l.sw 96(r1),r24
- l.sw 100(r1),r25
- l.sw 104(r1),r26
- l.sw 108(r1),r27
- l.sw 112(r1),r28
- l.sw 116(r1),r29
- l.sw 120(r1),r30
- l.sw 124(r1),r31
-
- /* Exception level related registers */
+ /* Store the registers (leave space for r0 although it isn't stored) */
+ l.sw OR1K_EC_GPR2(r1), r2
+ /* r3 is saved by BSP exception setup */
+ l.sw OR1K_EC_GPR4(r1), r4
+ l.sw OR1K_EC_GPR5(r1), r5
+ l.sw OR1K_EC_GPR6(r1), r6
+ l.sw OR1K_EC_GPR7(r1), r7
+ l.sw OR1K_EC_GPR8(r1), r8
+ l.sw OR1K_EC_GPR9(r1), r9
+ l.sw OR1K_EC_GPR10(r1), r10
+ l.sw OR1K_EC_GPR11(r1), r11
+ l.sw OR1K_EC_GPR12(r1), r12
+ l.sw OR1K_EC_GPR13(r1), r13
+ l.sw OR1K_EC_GPR14(r1), r14
+ l.sw OR1K_EC_GPR15(r1), r15
+ l.sw OR1K_EC_GPR16(r1), r16
+ l.sw OR1K_EC_GPR17(r1), r17
+ l.sw OR1K_EC_GPR18(r1), r18
+ l.sw OR1K_EC_GPR19(r1), r19
+ l.sw OR1K_EC_GPR20(r1), r20
+ l.sw OR1K_EC_GPR21(r1), r21
+ l.sw OR1K_EC_GPR22(r1), r22
+ l.sw OR1K_EC_GPR23(r1), r23
+ l.sw OR1K_EC_GPR24(r1), r24
+ l.sw OR1K_EC_GPR25(r1), r25
+ l.sw OR1K_EC_GPR26(r1), r26
+ l.sw OR1K_EC_GPR27(r1), r27
+ l.sw OR1K_EC_GPR28(r1), r28
+ l.sw OR1K_EC_GPR29(r1), r29
+ l.sw OR1K_EC_GPR30(r1), r30
+ l.sw OR1K_EC_GPR31(r1), r31
/* EPCR */
l.mfspr r13, r0, CPU_OR1K_SPR_EPCR0
- l.sw 128(r1), r13 /* epcr */
+ l.sw OR1K_EC_EPCR0(r1), r13
/* EEAR */
l.mfspr r13, r0, CPU_OR1K_SPR_EEAR0
- l.sw 132(r1), r13 /* eear */
+ l.sw OR1K_EC_EEAR0(r1), r13
/* ESR */
l.mfspr r13, r0, CPU_OR1K_SPR_ESR0
- l.sw 136(r1), r13 /* esr */
+ l.sw OR1K_EC_ESR0(r1), r13
/* Increment nesting level */
l.movhi r6, hi(ISR_NEST_LEVEL)
l.ori r6, r6, lo(ISR_NEST_LEVEL)
+ l.lwz r5, 0(r6)
+ l.addi r5, r5, 1
+ l.sw 0(r6), r5
- /* Disable multitasking */
+ /* Disable multitasking / thread dispatching */
l.movhi r8, hi(THREAD_DISPATCH_DISABLE_LEVEL)
l.ori r8, r8, lo(THREAD_DISPATCH_DISABLE_LEVEL)
-
- l.lwz r5, 0(r6)
l.lwz r7, 0(r8)
- l.addi r5, r5, 1
l.addi r7, r7, 1
- l.sw 0(r6), r5
l.sw 0(r8), r7
- /* Save interrupted task stack pointer */
- l.addi r4, r1, 340
- l.sw 4(r1), r4
+ /* Find installed handler */
+ l.add r11, r3, r0
+ l.slli r11, r11, 2
+ l.addi r11, r11, lo(bsp_start_vector_table_begin)
+ l.lwz r11, 0(r11)
- /* Save interrupted task r3 (first arg) value */
- l.addi r4, r1, 140
- l.lwz r4, 0(r4)
- l.sw 12(r1), r4
+ /* Save interrupted task stack pointer for exception frame diagnostics */
+ l.addi r8, r1, REDZONE_SIZE
+ l.addi r8, r8, EX_FRAME_SIZE
+ l.sw 4(r1), r8
- /* Keep r1 (Exception frame address) in r14 */
- l.add r14, r1, r0
-
- /* Call the exception handler from vector table */
-
- /* First function arg for C handler is vector number,
- * and the second is a pointer to exception frame.
+ /* First function arg for C handler is vector number (already there),
+ * and the second is a pointer to the exception frame.
*/
- l.add r13, r3, r0
- l.add r4, r1, r0
- l.slli r13, r13, 2
- l.addi r13, r13, lo(bsp_start_vector_table_begin)
- l.lwz r13, 0(r13)
+ l.add r4, r1, r0
+
+ /* Keep r1 (exception frame address) in r14 */
+ l.add r14, r1, r0
/* Do not switch stacks if we are in a nested interrupt. At
* this point r5 should be holding ISR_NEST_LEVEL value.
*/
l.sfgtui r5, 1
- l.bf jump_to_c_handler
+ l.bf jump_to_c_handler
l.nop
/* Switch to RTEMS dedicated interrupt stack */
@@ -128,35 +123,35 @@ PUBLIC(_ISR_Handler)
l.lwz r1, 0(r1)
jump_to_c_handler:
- l.jalr r13
+ /* Call the exception handler from vector table */
+ l.jalr r11
l.nop
- /* Switch back to the interrupted task stack */
- l.add r1, r14, r0
+ /* Switch back to the interrupted task stack (if changed) */
+ l.add r1, r14, r0
/* Decrement nesting level */
l.movhi r6, hi(ISR_NEST_LEVEL)
l.ori r6, r6, lo(ISR_NEST_LEVEL)
+ l.lwz r5, 0(r6)
+ l.addi r5, r5, -1
+ l.sw 0(r6), r5
/* Enable multitasking */
l.movhi r8, hi(THREAD_DISPATCH_DISABLE_LEVEL)
l.ori r8, r8, lo(THREAD_DISPATCH_DISABLE_LEVEL)
-
- l.lwz r5, 0(r6)
l.lwz r7, 0(r8)
- l.addi r5, r5, -1
l.addi r7, r7, -1
- l.sw 0(r6), r5
l.sw 0(r8), r7
/* Check if _ISR_Nest_level > 0 */
l.sfgtui r5, 0
- l.bf exception_frame_restore
+ l.bf exception_frame_restore
l.nop
/* Check if _Thread_Dispatch_disable_level > 0 */
l.sfgtui r7, 0
- l.bf exception_frame_restore
+ l.bf exception_frame_restore
l.nop
/* Check if dispatch needed */
@@ -172,58 +167,53 @@ jump_to_c_handler:
l.jalr r13
l.nop
- SYM(exception_frame_restore):
-
- /* Exception level related registers */
-
+SYM(exception_frame_restore):
/* EPCR */
- l.lwz r13, 128(r1)
+ l.lwz r13, OR1K_EC_EPCR0(r1)
l.mtspr r0, r13, CPU_OR1K_SPR_EPCR0
/* EEAR */
- l.lwz r13, 132(r1)
+ l.lwz r13, OR1K_EC_EEAR0(r1)
l.mtspr r0, r13, CPU_OR1K_SPR_EEAR0
/* ESR */
- l.lwz r13, 136(r1)
+ l.lwz r13, OR1K_EC_ESR0(r1)
l.mtspr r0, r13, CPU_OR1K_SPR_ESR0
- l.lwz r2, 8(r1)
- l.lwz r3, 12(r1)
- l.lwz r4, 16(r1)
- l.lwz r5, 20(r1)
- l.lwz r6, 24(r1)
- l.lwz r7, 28(r1)
- l.lwz r8, 32(r1)
- l.lwz r9, 36(r1)
- l.lwz r10, 40(r1)
- l.lwz r11, 44(r1)
- l.lwz r12, 48(r1)
- l.lwz r13, 52(r1)
- l.lwz r14, 56(r1)
- l.lwz r15, 60(r1)
- l.lwz r16, 64(r1)
- l.lwz r17, 68(r1)
- l.lwz r18, 72(r1)
- l.lwz r19, 76(r1)
- l.lwz r20, 80(r1)
- l.lwz r21, 84(r1)
- l.lwz r22, 88(r1)
- l.lwz r23, 92(r1)
- l.lwz r24, 96(r1)
- l.lwz r25, 100(r1)
- l.lwz r26, 104(r1)
- l.lwz r27, 108(r1)
- l.lwz r28, 112(r1)
- l.lwz r29, 116(r1)
- l.lwz r30, 120(r1)
- l.lwz r31, 124(r1)
-
- /* Unwind exception frame */
- l.addi r1, r1, 140
-
- /* Red-zone */
- l.addi r1, r1, 200
+ /* Restore GPRs */
+ l.lwz r2, OR1K_EC_GPR2(r1)
+ l.lwz r3, OR1K_EC_GPR3(r1)
+ l.lwz r4, OR1K_EC_GPR4(r1)
+ l.lwz r5, OR1K_EC_GPR5(r1)
+ l.lwz r6, OR1K_EC_GPR6(r1)
+ l.lwz r7, OR1K_EC_GPR7(r1)
+ l.lwz r8, OR1K_EC_GPR8(r1)
+ l.lwz r9, OR1K_EC_GPR9(r1)
+ l.lwz r10, OR1K_EC_GPR10(r1)
+ l.lwz r11, OR1K_EC_GPR11(r1)
+ l.lwz r12, OR1K_EC_GPR12(r1)
+ l.lwz r13, OR1K_EC_GPR13(r1)
+ l.lwz r14, OR1K_EC_GPR14(r1)
+ l.lwz r15, OR1K_EC_GPR15(r1)
+ l.lwz r16, OR1K_EC_GPR16(r1)
+ l.lwz r17, OR1K_EC_GPR17(r1)
+ l.lwz r18, OR1K_EC_GPR18(r1)
+ l.lwz r19, OR1K_EC_GPR19(r1)
+ l.lwz r20, OR1K_EC_GPR20(r1)
+ l.lwz r21, OR1K_EC_GPR21(r1)
+ l.lwz r22, OR1K_EC_GPR22(r1)
+ l.lwz r23, OR1K_EC_GPR23(r1)
+ l.lwz r24, OR1K_EC_GPR24(r1)
+ l.lwz r25, OR1K_EC_GPR25(r1)
+ l.lwz r26, OR1K_EC_GPR26(r1)
+ l.lwz r27, OR1K_EC_GPR27(r1)
+ l.lwz r28, OR1K_EC_GPR28(r1)
+ l.lwz r29, OR1K_EC_GPR29(r1)
+ l.lwz r30, OR1K_EC_GPR30(r1)
+ l.lwz r31, OR1K_EC_GPR31(r1)
+
+ /* Unwind exception frame and redzone */
+ l.addi r1, r1, (EX_FRAME_SIZE + REDZONE_SIZE)
l.rfe
l.nop
--
1.7.10.4
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