Mailbox RPi patch and rtems_cache_* probably broken on RPi

[Sebastian Huber]

On 23/06/16 17:44, Gedare Bloom wrote:
> This could explain a number of problems reported by students trying to
> get their RPi peripherals working. The cache manager has never been a
> robust and complete implementation. I think it must be carefully
> looked at across targets (easier when we delete obsolete
> architectures!).
>
> It looks like every arch's cache_.h should be defining
> CPU_DATA_CACHE_ALIGNMENT if it has a data cache. This requirement has
> probably never been documented properly somewhere, and it rightly may
> belong in the score/cpu/*/rtems/score/cpu.h.
>
> I'm not sure what you mean by maximal cache alignment.

We have two tests for the cache manager spcache01 and smpcache01. It is 
not easy to write a proper test for the cache manager, so these tests 
are far from being perfect, however they check the common cases. Every 
BSP with at least 4MiB of RAM should be able to pass all tests.

-- 
Sebastian Huber, embedded brains GmbH

Address : Dornierstr. 4, D-82178 Puchheim, Germany
Phone   : +49 89 189 47 41-16
Fax     : +49 89 189 47 41-09
E-Mail  : sebastian.huber at embedded-brains.de
PGP     : Public key available on request.

Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.