arm/xilinx_zynq: Disable the MMU on startup and CPU CP15 recognized cache levels

Pavel Pisa ppisa4lists at
Thu Sep 1 09:49:01 UTC 2016

Hello Chrisn,

thanks for commiting. Have you tested code on Zynq in SMP RTEMS build?
I have tested only on Zynq UP for now.

I have run test to document which cache levels are maintained
by CP15 by different ARM chips. I print only data and unified
ones ones because it is enough for levels and sharing

Xilinx Zynq

cache levels:
  clidr 0x09200003 loc 1
  level 0 ctype 3 size 32768
  level 0 ccsidr 0x701FE019
  line_power 0x05 associativity 0x04 way_shift 0x1E

Raspberry Pi v2 BCM2836

cache type 0x84448003
cache levels:
  clidr 0x0A200023 loc 2
  level 0 ctype 3
  level 0 ccsidr 0x700FE01A size 32768
  line_power 0x06 associativity 0x04 way_shift 0x1E
  level 1 ctype 4
  level 1 ccsidr 0x707FE03A size 524288
  line_power 0x06 associativity 0x08 way_shift 0x1D

Raspberry Pi v1 BCM2835

cache type 0x1D152152
cache levels:
  level 1 ctype 14 size 16384
  line_power 0x05 associativity 0x08 size_power 0x0E page aliasing 0

RPi1 uses old (pre ARMv7) format.

May it be, we should add debug function to print detailed
cache organization into RTEMS ARM support files.

Best wishes,


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