RISC-V interrupts in HiFive1

[Denis Obrezkov]

Hello all,

at the end of the GSoC I've found out that interrupts in my BSP
weren't properly enabled/disabled globally.
This happens because my work is based on the Hesham's
BSP for RISC-V and it was done for the previous version of ISA.
Thus, the Hesham's interrupt enabling/disabling instructions did
nothing in my version of ISA.
I've tried to fix this issue, but without much of success.

-- 
Regards, Denis Obrezkov
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