[PATCH v2 07/15] HiFive1: add irq dispatching function
Hesham Almatary
heshamelmatary at gmail.com
Wed Aug 23 00:41:06 UTC 2017
On Tue, Aug 22, 2017 at 9:56 AM, Denis Obrezkov <denisobrezkov at gmail.com> wrote:
> ---
> c/src/lib/libbsp/riscv32/hifive1/include/irq.h | 12 +++
> c/src/lib/libbsp/riscv32/hifive1/irq/irq.c | 86 ++++++++++++++++++++++
> c/src/lib/libbsp/riscv32/hifive1/start/start.S | 3 +-
> .../score/cpu/riscv32/rtems/score/riscv-utility.h | 26 +++++++
> 4 files changed, 126 insertions(+), 1 deletion(-)
> create mode 100644 c/src/lib/libbsp/riscv32/hifive1/irq/irq.c
>
> diff --git a/c/src/lib/libbsp/riscv32/hifive1/include/irq.h b/c/src/lib/libbsp/riscv32/hifive1/include/irq.h
> index 67a781f..46d29c7 100644
> --- a/c/src/lib/libbsp/riscv32/hifive1/include/irq.h
> +++ b/c/src/lib/libbsp/riscv32/hifive1/include/irq.h
> @@ -11,6 +11,8 @@
> * Copyright (c) 2015 University of York.
> * Hesham ALMatary <hmka501 at york.ac.uk>
> *
> + * Copyright (c) 2017 Denis Obrezkov <denisobrezkov at gmail.com>
> + *
> * Redistribution and use in source and binary forms, with or without
> * modification, are permitted provided that the following conditions
> * are met:
> @@ -52,6 +54,16 @@
> #define MCAUSE_MTIME 0x7
> #define MCAUSE_MEXT 0xB
>
> +#define MIE_MSWI (1 << MCAUSE_MSWI)
> +#define MIE_MTIME (1 << MCAUSE_MTIME)
> +#define MIE_MEXT (1 << MCAUSE_MEXT)
> +
> +/*
> + * Memory mapped timer, timer comparator and software interrupt registers.
> + */
> +#define MTIMECMP ((volatile uint64_t *)0x02004000)
> +#define MTIME ((volatile uint64_t *)0x0200bff8)
> +#define MSIP_REG ((volatile uint32_t *) 0x02000000)
>
> #endif /* ASM */
> #endif /* LIBBSP_GENERIC_RISCV_IRQ_H */
> diff --git a/c/src/lib/libbsp/riscv32/hifive1/irq/irq.c b/c/src/lib/libbsp/riscv32/hifive1/irq/irq.c
> new file mode 100644
> index 0000000..fadfdb7
> --- /dev/null
> +++ b/c/src/lib/libbsp/riscv32/hifive1/irq/irq.c
> @@ -0,0 +1,86 @@
> +/**
> + * @file
> + *
> + * @ingroup riscv_interrupt
> + *
> + * @brief Interrupt support.
> + */
> +
> +/*
> + * RISCV CPU Dependent Source
> + *
> + * Copyright (c) 2015 University of York.
> + * Hesham ALMatary <hmka501 at york.ac.uk>
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions
> + * are met:
> + * 1. Redistributions of source code must retain the above copyright
> + * notice, this list of conditions and the following disclaimer.
> + * 2. Redistributions in binary form must reproduce the above copyright
> + * notice, this list of conditions and the following disclaimer in the
> + * documentation and/or other materials provided with the distribution.
> + *
> + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
> + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
> + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
> + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
> + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
> + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
> + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
> + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
> + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
> + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
> + * SUCH DAMAGE.
> + */
> +
> +#include <bsp/fe310.h>
> +#include <bsp/irq.h>
> +#include <bsp/irq-generic.h>
> +
> +/* Almost all of the jobs that the following functions should
> + * do are implemented in cpukit
> + */
> +
> +void bsp_interrupt_handler_default(rtems_vector_number vector)
> +{
> + printk("spurious interrupt: %u\n", vector);
> +}
> +
> +rtems_status_code bsp_interrupt_facility_initialize()
> +{
> + return 0;
> +}
> +
> +rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector)
> +{
> + return 0;
> +}
> +
> +rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector)
> +{
> + return 0;
> +}
> +
> +/*
> + * FIXME: only timer intrrupt is handled
> + */
> +void handle_trap (uint32_t cause)
> +{
> + if (cause & MCAUSE_INT) {
> + /* an interrupt occurred */
> + if ((cause & MCAUSE_MTIME) == MCAUSE_MTIME) {
> + /* Timer interrupt */
> + (*MTIMECMP) = (*MTIME) + FE310_CLOCK_PERIOD;
> + bsp_interrupt_handler_table[1].handler(bsp_interrupt_handler_table[1].arg);
> + } else if ((cause & MCAUSE_MEXT) == MCAUSE_MEXT) {
> + /*External interrupt */
> + } else if ((cause & MCAUSE_MSWI) == MCAUSE_MSWI) {
> + /* Software interrupt */
> + *MSIP_REG = 0;
> + }
> + } else {
> + /* an exception occurred */
> + }
> +
> +}
> diff --git a/c/src/lib/libbsp/riscv32/hifive1/start/start.S b/c/src/lib/libbsp/riscv32/hifive1/start/start.S
> index 5d0899c..b3fb3f3 100644
> --- a/c/src/lib/libbsp/riscv32/hifive1/start/start.S
> +++ b/c/src/lib/libbsp/riscv32/hifive1/start/start.S
> @@ -209,7 +209,8 @@ trap_entry:
> csrr t0, mcause
> SREG t0, 33*REGBYTES(sp)
>
> - call handle_trap_new
> + mv a0, t0
> + call handle_trap
>
> LREG t0, 32*REGBYTES(sp)
> csrw mepc, t0
> diff --git a/cpukit/score/cpu/riscv32/rtems/score/riscv-utility.h b/cpukit/score/cpu/riscv32/rtems/score/riscv-utility.h
> index c45b05f..8abc0bd 100644
> --- a/cpukit/score/cpu/riscv32/rtems/score/riscv-utility.h
> +++ b/cpukit/score/cpu/riscv32/rtems/score/riscv-utility.h
> @@ -14,4 +14,30 @@
> #ifndef _RTEMS_SCORE_RISCV_UTILITY_H
> #define _RTEMS_SCORE_RISCV_UTILITY_H
>
> +#define read_csr(reg) ({ unsigned long __tmp; \
> + asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
> + __tmp; })
> +
> +#define write_csr(reg, val) \
> + asm volatile ("csrw " #reg ", %0" :: "r"(val))
> +
> +#define swap_csr(reg, val) ({ long __tmp; \
> + asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
> + __tmp; })
> +
> +#define set_csr(reg, bit) ({ unsigned long __tmp; \
> + if (__builtin_constant_p(bit) && (bit) < 32) \
> + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
> + else \
> + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
> + __tmp; })
> +
> +#define clear_csr(reg, bit) ({ unsigned long __tmp; \
> + if (__builtin_constant_p(bit) && (bit) < 32) \
> + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
> + else \
> + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
> + __tmp; })
> +
> +
Would you add the license/comment for the file/code this is originally
copied from? Similarally for all of the other patches. In RTEMS, GPLv2
is used, it might conflict with other types of licenses.
> #endif /* _RTEMS_SCORE_RISCV_UTILITY_H */
> --
> 2.1.4
>
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--
Hesham
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