Basic RISC-V 32-bit tool chain

[Gedare Bloom]

Denis,

On Wed, Aug 23, 2017 at 1:23 AM, Sebastian Huber
<sebastian.huber at embedded-brains.de> wrote:
> On 23/08/17 04:16, Chris Johns wrote:
>
>> On 23/08/2017 11:34, Hesham Almatary wrote:
>>>
>>> Hi all,
>>>
>>> I am reporting my efforts on this thread:
>>>
>>> * RSB/master/vanilla: riscv32 tested and builds just fine with no
>>> changes from my side.
>>
>> Hesham, can you please update rtems-all.bset to add RISC-V? The change is
>> OK'ed
>> by me so please just push it.
>
>
> Sorry for forgetting this, I updated the RSB.
>
>>
>>> * RTEMS/riscv32: priv-1.10 branch - rebased with rtems/master, fixed
>>> errors, and pushed to GitHub [1].
>>> * RTEMS/Spike: BSP builds sample tests and tested hello/ticker on
>>> Spike simulator.
>>
>> Hesham, once you are happy with the changes and the reviews have finished
>> please
>> push to master.
>>
>> Is there a ticket for adding the RISC-V to RTEMS? If not please create a
>> ticket
>> and please reference it in a patch or patches so the release notes have an
>> entry.
>
>
> I added a ticket:
>
> http://devel.rtems.org/ticket/3109
>
Refer to this ticket ("Updates #3109.") in all of your patches that
create the riscv port and initial bsp(s)

> --
> Sebastian Huber, embedded brains GmbH
>
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>
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>
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