RISC-V interrupt vectoring

[Denis Obrezkov]

Hello all,
I am trying to enable vectored interrupts on my HiFive1 board.
I was able to install interrupt vector base address, but it didn't work.
And I wasn't able to generate a software interrupt.
Though, it seems that interrupts works - at some moment of execution,
I catch the exception 'Illegal instruction', and this exception is from
dummy_timecounter().

Hesham, do you know something about the possibility of interrupt
vectoring? I can see in E31-coreplex manual that vectoring can be
turned on, but I don't whether this functionality was implemented in
FE310-core.

Also, do you know how to generate a software interrupt?

I've also created a topic on a sifive forum with some description:
https://forums.sifive.com/t/is-interrupt-vectoring-available-in-hifive1/622

-- 
Regards, Denis Obrezkov
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