RISC-V interrupt vectoring

[Hesham Almatary]

You can have a look at riscv-pk [1] as a RISC-V reference how to
handle interrupts. RTEMS-wise, you can look at or1k and ARM code and
how the platform-dependent interrupt handling code is linked to
platform-independent one.

mcause value can be used as an index to a software vector table that you set up.

Why do you need software interrupts? GSoC-wise, I thought the plan was
to develop UART/Console driver (which doesn't need interrupts), and
use simulated ticker, as a first step. Then it will be easier to
debug/proceed from there with interrupt handling code.

[1] https://github.com/riscv/riscv-pk/blob/master/machine/mentry.S

On Mon, Jul 3, 2017 at 9:53 AM, Denis Obrezkov <denisobrezkov at gmail.com> wrote:
> Hello all,
> I am trying to enable vectored interrupts on my HiFive1 board.
> I was able to install interrupt vector base address, but it didn't work.
> And I wasn't able to generate a software interrupt.
> Though, it seems that interrupts works - at some moment of execution,
> I catch the exception 'Illegal instruction', and this exception is from
> dummy_timecounter().
>
> Hesham, do you know something about the possibility of interrupt
> vectoring? I can see in E31-coreplex manual that vectoring can be
> turned on, but I don't whether this functionality was implemented in
> FE310-core.
>
> Also, do you know how to generate a software interrupt?
>
> I've also created a topic on a sifive forum with some description:
> https://forums.sifive.com/t/is-interrupt-vectoring-available-in-hifive1/622
>
> --
> Regards, Denis Obrezkov



-- 
Hesham