[PATCH 01/17] bsps/m68k/shared/cache/cache.h: Fix warnings and clean up

[Joel Sherrill]

---
 bsps/m68k/shared/cache/cache.h | 81 ++++++++++++++++++++++--------------------
 1 file changed, 43 insertions(+), 38 deletions(-)

diff --git a/bsps/m68k/shared/cache/cache.h b/bsps/m68k/shared/cache/cache.h
index 2fa78b6..18797d4 100644
--- a/bsps/m68k/shared/cache/cache.h
+++ b/bsps/m68k/shared/cache/cache.h
@@ -54,7 +54,7 @@
  *  Used to set bits in the cacr.
  */
 #define _CPU_CACR_OR(mask)                                         \
-	{                                                                \
+  {                                                                \
   register unsigned long _value = mask;                            \
   register unsigned long _ctl = 0;                                 \
   __asm__ volatile ( "movec %%cacr, %0;           /* read the cacr */  \
@@ -76,37 +76,39 @@
 
 /* Only the mc68030 has a data cache; it is writethrough only. */
 
-void _CPU_cache_flush_1_data_line ( const void * d_addr ) {}
-void _CPU_cache_flush_entire_data ( void ) {}
+RTEMS_INLINE_ROUTINE void _CPU_cache_flush_1_data_line(const void * d_addr) {}
+RTEMS_INLINE_ROUTINE void _CPU_cache_flush_entire_data(void) {}
 
-void _CPU_cache_invalidate_1_data_line (
-  const void * d_addr )
+RTEMS_INLINE_ROUTINE void _CPU_cache_invalidate_1_data_line(
+  const void * d_addr
+)
 {
   void * p_address = (void *) _CPU_virtual_to_physical( d_addr );
   __asm__ volatile ( "movec %0, %%caar" :: "a" (p_address) );      /* write caar */
   _CPU_CACR_OR(0x00000400);
 }
 
-void _CPU_cache_invalidate_entire_data ( void )
+RTEMS_INLINE_ROUTINE void _CPU_cache_invalidate_entire_data(void)
 {
   _CPU_CACR_OR( 0x00000800 );
 }
 
-void _CPU_cache_freeze_data ( void )
+RTEMS_INLINE_ROUTINE void _CPU_cache_freeze_data(void)
 {
   _CPU_CACR_OR( 0x00000200 );
 }
 
-void _CPU_cache_unfreeze_data ( void )
+RTEMS_INLINE_ROUTINE void _CPU_cache_unfreeze_data(void)
 {
   _CPU_CACR_AND( 0xFFFFFDFF );
 }
 
-void _CPU_cache_enable_data ( void )
+RTEMS_INLINE_ROUTINE void _CPU_cache_enable_data(void)
 {
   _CPU_CACR_OR( 0x00000100 );
 }
-void _CPU_cache_disable_data (	void )
+
+RTEMS_INLINE_ROUTINE void _CPU_cache_disable_data(void)
 {
   _CPU_CACR_AND( 0xFFFFFEFF );
 }
@@ -115,35 +117,36 @@ void _CPU_cache_disable_data (	void )
 
 /* Both the 68020 and 68030 have instruction caches */
 
-void _CPU_cache_invalidate_1_instruction_line (
-  const void * d_addr )
+RTEMS_INLINE_ROUTINE void _CPU_cache_invalidate_1_instruction_line(
+  const void * d_addr
+)
 {
   void * p_address = (void *) _CPU_virtual_to_physical( d_addr );
-  __asm__ volatile ( "movec %0, %%caar" :: "a" (p_address) );      /* write caar */
+  __asm__ volatile ( "movec %0, %%caar" :: "a" (p_address) ); /* write caar */
   _CPU_CACR_OR( 0x00000004 );
 }
 
-void _CPU_cache_invalidate_entire_instruction ( void )
+RTEMS_INLINE_ROUTINE void _CPU_cache_invalidate_entire_instruction(void)
 {
   _CPU_CACR_OR( 0x00000008 );
 }
 
-void _CPU_cache_freeze_instruction ( void )
+RTEMS_INLINE_ROUTINE void _CPU_cache_freeze_instruction(void)
 {
   _CPU_CACR_OR( 0x00000002);
 }
 
-void _CPU_cache_unfreeze_instruction ( void )
+RTEMS_INLINE_ROUTINE void _CPU_cache_unfreeze_instruction(void)
 {
   _CPU_CACR_AND( 0xFFFFFFFD );
 }
 
-void _CPU_cache_enable_instruction ( void )
+RTEMS_INLINE_ROUTINE void _CPU_cache_enable_instruction(void)
 {
   _CPU_CACR_OR( 0x00000001 );
 }
 
-void _CPU_cache_disable_instruction (	void )
+RTEMS_INLINE_ROUTINE void _CPU_cache_disable_instruction(void)
 {
   _CPU_CACR_AND( 0xFFFFFFFE );
 }
@@ -152,64 +155,66 @@ void _CPU_cache_disable_instruction (	void )
 #elif ( defined(__mc68040__) || defined (__mc68060__) )
 
 /* Cannot be frozen */
-void _CPU_cache_freeze_data ( void ) {}
-void _CPU_cache_unfreeze_data ( void ) {}
-void _CPU_cache_freeze_instruction ( void ) {}
-void _CPU_cache_unfreeze_instruction ( void ) {}
+RTEMS_INLINE_ROUTINE void _CPU_cache_freeze_data(void) {}
+RTEMS_INLINE_ROUTINE void _CPU_cache_unfreeze_data(void) {}
+RTEMS_INLINE_ROUTINE void _CPU_cache_freeze_instruction(void) {}
+RTEMS_INLINE_ROUTINE void _CPU_cache_unfreeze_instruction(void) {}
 
-void _CPU_cache_flush_1_data_line (
-  const void * d_addr )
+RTEMS_INLINE_ROUTINE void _CPU_cache_flush_1_data_line(
+  const void * d_addr
+)
 {
   void * p_address = (void *) _CPU_virtual_to_physical( d_addr );
   __asm__ volatile ( "cpushl %%dc,(%0)" :: "a" (p_address) );
 }
 
-void _CPU_cache_invalidate_1_data_line (
-  const void * d_addr )
+RTEMS_INLINE_ROUTINE void _CPU_cache_invalidate_1_data_line(
+  const void * d_addr
+)
 {
   void * p_address = (void *) _CPU_virtual_to_physical( d_addr );
   __asm__ volatile ( "cinvl %%dc,(%0)" :: "a" (p_address) );
 }
 
-void _CPU_cache_flush_entire_data ( void )
+RTEMS_INLINE_ROUTINE void _CPU_cache_flush_entire_data(void)
 {
-	asm volatile ( "cpusha %%dc" :: );
+  __asm__ volatile ( "cpusha %%dc" :: );
 }
 
-void _CPU_cache_invalidate_entire_data ( void )
+RTEMS_INLINE_ROUTINE void _CPU_cache_invalidate_entire_data(void)
 {
-	asm volatile ( "cinva %%dc" :: );
+  __asm__ volatile ( "cinva %%dc" :: );
 }
 
-void _CPU_cache_enable_data ( void )
+RTEMS_INLINE_ROUTINE void _CPU_cache_enable_data(void)
 {
   _CPU_CACR_OR( 0x80000000 );
 }
 
-void _CPU_cache_disable_data ( void )
+RTEMS_INLINE_ROUTINE void _CPU_cache_disable_data(void)
 {
   _CPU_CACR_AND( 0x7FFFFFFF );
 }
 
-void _CPU_cache_invalidate_1_instruction_line (
+RTEMS_INLINE_ROUTINE void _CPU_cache_invalidate_1_instruction_line(
   const void * i_addr )
 {
   void * p_address = (void *)  _CPU_virtual_to_physical( i_addr );
   __asm__ volatile ( "cinvl %%ic,(%0)" :: "a" (p_address) );
 }
 
-void _CPU_cache_invalidate_entire_instruction ( void )
+RTEMS_INLINE_ROUTINE void _CPU_cache_invalidate_entire_instruction(void)
 {
-		asm volatile ( "cinva %%ic" :: );
+  __asm__ volatile ( "cinva %%ic" :: );
 }
 
-void _CPU_cache_enable_instruction ( void )
+RTEMS_INLINE_ROUTINE void _CPU_cache_enable_instruction(void)
 {
   _CPU_CACR_OR( 0x00008000 );
 }
 
-void _CPU_cache_disable_instruction ( void )
+RTEMS_INLINE_ROUTINE void _CPU_cache_disable_instruction(void)
 {
-	_CPU_CACR_AND( 0xFFFF7FFF );
+  _CPU_CACR_AND( 0xFFFF7FFF );
 }
 #endif
-- 
1.8.3.1