PATCH: Multiprocessor support for SIS simulator

[Jiri Gaisler]

I have have attached a patch for RSB that will enable SMP support for
the sis simulator. This is done by pulling in a second sis patch on top
of the existing one, containing the SMP feature. To enable SMP
operation, start sis with -m <n> where n is between 2 and 4:

$ sparc-rtems5-sis -leon3 -m 4

 SIS - SPARC instruction simulator 2.9,  copyright Jiri Gaisler 1995
 Bug-reports to jiri at gaisler.se

 LEON3 emulation enabled, 4 cpus online, delta 50 clocks

sis>

I have updated the README files in sis to reflect the new features.
Debugging in gdb works as before, but breakpoints are global until I
manage to add RTEMS threads awareness to sis.

A second (simple) patch is attached for leon3-sis.ini in rtems-tools,
just to allow rtems-test to run the SMP tests.

I will now move to gdb-8.2+ and merge RISCV support to sis.

Jiri.

-------------- next part --------------
A non-text attachment was scrubbed...
Name: rtems-source-builder-sismp.diff
Type: text/x-patch
Size: 899 bytes
Desc: not available
URL: <http://lists.rtems.org/pipermail/devel/attachments/20181216/dc072f5c/attachment.bin>
-------------- next part --------------
A non-text attachment was scrubbed...
Name: rtems-tools-sismp.diff
Type: text/x-patch
Size: 486 bytes
Desc: not available
URL: <http://lists.rtems.org/pipermail/devel/attachments/20181216/dc072f5c/attachment-0001.bin>