Status of smptests ...?
sebastian.huber at embedded-brains.de
Wed Dec 12 05:07:55 UTC 2018
----- Am 11. Dez 2018 um 22:08 schrieb Jiri Gaisler jiri at gaisler.se:
> On 12/11/18 3:39 PM, Sebastian Huber wrote:
>> Hello Jiri,
>> On 11/12/2018 15:24, Sebastian Huber wrote:
>>> Hello Jiri,
>>> On 11/12/2018 15:15, Jiri Gaisler wrote:
>>>> What is the status of the smptests of RTEMS 5 ?
>>>> I have added SMP capability to the sis simulator, and have tested it
>>>> with the smptests from rtems git. I have noticed that the reference
>>>> output (*.scn) are not equivalent to what the simulator or real
>>>> outputs. It seems that the cpus are numbered backwards compared to the
>>>> .scn files.
>>> the .scn files are not up to date. Also the test output is quite test
>>> dependent and repeated test runs my produce different output.
>>> The best method to check if a test passed is to check if the
>>> *** END OF TEST XYZ ***
>>> message is printed. Which real target did you use to run the tests? I
>>> will do a test run tomorrow on a N2X.
>> attached is a run of the smptests on a N2X board.
> Thanks, that helped. I can run all SMP tests successfully now on my FPGA
> hardware. On the simulator, I have about 35 passed and 20 failed. Most
> of the fails are hangs during initialization, I suspect a problem with
> the MP interrupt controller or timer unit. I will keep you posted on the
> progress. FYI, I have attached the log from the successful runs.
The passing tests are the harmless ones. I would try to concentrate on these three tests:
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