MMU was Re: Contribute to a project under GSOC 2018

[Hesham Almatary]

On Sun, Mar 4, 2018 at 10:20 AM, Joel Sherrill <joel at rtems.org> wrote:
>
>
> On Mar 3, 2018 12:16 PM, "Abhinav Jain" <jainab.2009 at gmail.com> wrote:
>
> Sir/Madam,
>
> I am Abhinav Jain, a second-year engineering student from Delhi, India. I
> have been working in Linux Kernel Development, I have been writing small
> drivers and have a good knowledge of the operating system.
> I have been studying about Memory Protection project(ticket #2904) for
> around a month and found it really interesting. I studied about POSIX, MMU
> support in various other architecture and the memory protection APIs in
> various operating systems.I have been discussing the same on the mailing
> list.
> I also solved an issue (#2522) around a week ago to gain some hands-on code.
>
>
> Welcome aboard.
>
>
> I would like to work on the Memory Protection project under GSOC 2018, so I
> request you to please guide me regarding the steps to be followed.
>
>
> Gedare conceived of what's there be so I cc'ed him. My recollection is that
> there were specific things he wanted to change and when that was addressed,
> providing support for arenas on multiple architecture is desirable
>
+1

There might be an opportunity to port RTEMS to RISC-V's Supervisor
Mode which will need MMU support (currently it only runs on M-Mode
which doesn't have MMU). Both QEMU and Spike simulators support
S-Mode.

>
>
> Thanks and Regards
> Abhinav Jain
>
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-- 
Hesham