[PATCH 2/3] Add ARM Paravirtualization support

[Joel Sherrill]

Closes #3305.
---
 cpukit/score/cpu/arm/cpu_asm.S                     |  3 +-
 cpukit/score/cpu/arm/headers.am                    |  1 +
 cpukit/score/cpu/arm/include/rtems/score/cpu.h     |  9 +++
 .../score/cpu/arm/include/rtems/score/paravirt.h   | 75 ++++++++++++++++++++++
 4 files changed, 87 insertions(+), 1 deletion(-)
 create mode 100644 cpukit/score/cpu/arm/include/rtems/score/paravirt.h

diff --git a/cpukit/score/cpu/arm/cpu_asm.S b/cpukit/score/cpu/arm/cpu_asm.S
index f58b99d..39a756c 100644
--- a/cpukit/score/cpu/arm/cpu_asm.S
+++ b/cpukit/score/cpu/arm/cpu_asm.S
@@ -111,9 +111,10 @@ DEFINE_FUNCTION_ARM(_CPU_Context_switch)
 #endif
 
 #ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER
+  #ifndef ARM_DISABLE_THREAD_ID_REGISTER_USE
 	mcr	p15, 0, r3, c13, c0, 3
+  #endif
 #endif
-
 	str	r4, [r2, #PER_CPU_ISR_DISPATCH_DISABLE]
 
 	/* In ARMv5T and above the load of PC is an interworking branch */
diff --git a/cpukit/score/cpu/arm/headers.am b/cpukit/score/cpu/arm/headers.am
index 6325328..9bbc701 100644
--- a/cpukit/score/cpu/arm/headers.am
+++ b/cpukit/score/cpu/arm/headers.am
@@ -21,3 +21,4 @@ include_rtems_score_HEADERS += include/rtems/score/cpu.h
 include_rtems_score_HEADERS += include/rtems/score/cpu_asm.h
 include_rtems_score_HEADERS += include/rtems/score/cpuatomic.h
 include_rtems_score_HEADERS += include/rtems/score/cpuimpl.h
+include_rtems_score_HEADERS += include/rtems/score/paravirt.h
diff --git a/cpukit/score/cpu/arm/include/rtems/score/cpu.h b/cpukit/score/cpu/arm/include/rtems/score/cpu.h
index 15e3ac7..728a43c 100644
--- a/cpukit/score/cpu/arm/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/arm/include/rtems/score/cpu.h
@@ -30,6 +30,9 @@
 #define _RTEMS_SCORE_CPU_H
 
 #include <rtems/score/basedefs.h>
+#if defined(RTEMS_PARAVIRT)
+#include <rtems/score/paravirt.h>
+#endif
 #include <rtems/score/arm.h>
 
 #if defined(ARM_MULTILIB_ARCH_V4)
@@ -297,6 +300,11 @@ static inline void _ARM_Instruction_synchronization_barrier( void )
 #endif
 }
 
+#if defined(ARM_DISABLE_INLINE_ISR_DISABLE_ENABLE)
+uint32_t arm_interrupt_disable( void );
+void arm_interrupt_enable( uint32_t level );
+void arm_interrupt_flash( uint32_t level );
+#else
 static inline uint32_t arm_interrupt_disable( void )
 {
   uint32_t level;
@@ -387,6 +395,7 @@ static inline void arm_interrupt_flash( uint32_t level )
   );
 #endif
 }
+#endif  /* !ARM_DISABLE_INLINE_ISR_DISABLE_ENABLE */
 
 #define _CPU_ISR_Disable( _isr_cookie ) \
   do { \
diff --git a/cpukit/score/cpu/arm/include/rtems/score/paravirt.h b/cpukit/score/cpu/arm/include/rtems/score/paravirt.h
new file mode 100644
index 0000000..08fb8a0
--- /dev/null
+++ b/cpukit/score/cpu/arm/include/rtems/score/paravirt.h
@@ -0,0 +1,75 @@
+/**
+ * @file
+ *
+ * @brief ARM Paravirtualization Definitions
+ *
+ * This include file contains definitions pertaining to paravirtualization
+ * of the ARM port.
+ */
+
+/*
+ *  COPYRIGHT (c) 2018.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may in
+ *  the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+
+#ifndef RTEMS_PARAVIRT
+#error "This file should only be included with paravirtualization is enabled."
+#endif
+
+#ifndef _RTEMS_SCORE_PARAVIRT_H
+#define _RTEMS_SCORE_PARAVIRT_H
+
+/**
+ * @defgroup ParavirtARM Paravirtualization ARM Support
+ *
+ * @ingroup Score
+ *
+ * This handler encapulates the functionality (primarily conditional
+ * feature defines) related to paravirtualization on the ARM.
+ *
+ * Paravirtualization on the ARM makes the following assumptions:
+ *
+ *   - RTEMS executes in user space
+ *   - Interrupt enable/disable support using the MSR must be disabled
+ *     and replaced with BSP provided methods which are adapted to the
+ *     hosting environment.
+ */
+
+#ifndef ASM
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* !ASM */
+
+/**
+ * In a paravirtualized environment, RTEMS executes in user space
+ * and cannot disable/enable external exceptions (e.g. interrupts).
+ * The BSP which acts as an adapter to the hosting environment will
+ * provide the interrupt enable/disable methods.
+ */
+#define ARM_DISABLE_INLINE_ISR_DISABLE_ENABLE
+
+/**
+ * In a paravirtualized environment, RTEMS executes in user space
+ * and cannot write to the the Thread ID register which is normally
+ * used. CP15 C13 has three variants of a Thread ID register.
+ *
+ * - Opcode_2 = 2: This register is both user and privileged R/W accessible.
+ * - Opcode_2 = 3: This register is user read-only and privileged
+ *   R/W accessible.
+ * - Opcode_2 = 4: This register is privileged R/W accessible only.
+ */
+#define ARM_DISABLE_THREAD_ID_REGISTER_USE
+
+#endif
-- 
1.8.3.1