RISC-V Test Results

[Joel Sherrill]

On Fri, Aug 9, 2019, 5:39 AM Hesham Almatary <heshamelmatary at gmail.com>
wrote:

> Hi Joel,
>
>
> On Thu, 8 Aug 2019 at 14:34, Joel Sherrill <joel at rtems.org> wrote:
> >
> > Hi
> >
> > If you are subscribed to the build@ mailing list, then you saw the
> flurry of test
> > results from over night. I built every variant and ran the test suite
> with RTEMS
> > debug on and off.  Here are some observations:
> >
> > + rv64imafd only has one test pass
> I think you mean rv64imafd_medany by this? Which only has 1 test
> passing. Anyway, I had a look at your run command which provides
> --rtems-bsp=rv64imafd_medany_spike. However, rv64imafd BSP variant is
> the ones passed to the tester instead of rv64imafd_medany, which
> should definitely fail as the start address of this one is 0x70000000
> and Spike's default memory base t0 0x80000000.
>

Thanks for catching the typo. I have a script which distinguishes the same
bsp on different simulators.

Is the riscv support in upstream Qemu? I recall Jim Wilson mentioning it
had been. If so, updating our Qemu in the RSB would be good. As it is now,
there is no RSB Qemu with riscv

>
> > + rv64_iamd_medany only has one test pass
> > + Generally speaking, 17-19 tests failed or timed out on every variant
> with
> >    551-553 passing. It would be great for someone to mark the tests in
> the
> >    tcfg files as expected fails.
> >
> > Hopefully this gives someone incentive to look into the failures.
> >
> > I would also run them on qemu but I don't think we have an RSB recipe
> for a
> > Qemu with RISC-V support.
> >
> > --joel
>
>
>
> --
> Hesham
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.rtems.org/pipermail/devel/attachments/20190809/e75ee5b9/attachment-0002.html>