Zynq Ultrascale+

[Jeff Kubascik]

Hello Matthew,

On 12/8/2019 2:15 PM, Mathew Benson wrote:
> My new board arrived so I'm shelving the OcPoC (Zynq 7020) to focus on the
> new Zynq Ultrascale+.
> 
> https://shop.trenz-electronic.de/en/TE0820-03-2AI21FA-MPSoC-Module-with-Xilinx-Zynq-UltraScale-ZU2CG-1I-2-GByte-DDR4-SDRAM-4-x-5-cm
> 
> Has anybody ported RTEMS to the Zynq Ultrascale+?  I saw that
> "xilinx_zynqmp" is the arm family with "xilinx_zynqmp_ultra96" BSP.  Does
> this actually work?  Maybe this is a dumb question, but why is the
> xilinx_zynqmp_ultra96 BSP built using the arm-rtems5 toolchain?  It builds
> a 32 bit binary.  The Zynq Ultrascale is 64 bit.  The linux kernel built by
> the Xilinx Petalinux toolchain results in an aarch64 kernel.

I did the port to the Zynq UltraScale+ earlier this year, specifically for the
Ultra96 board. There is a readme file under bsps/arm/xilinx-zynqmp that
describes how to JTAG load an application using the Xilinx tools. This BSP
should work for any UltraScale+ board. The only caveat is the console is
configured to use UART1; depending on your board, you may need to change this to
UART0.

RTEMS doesn't have support for 64 bit ARM yet, so this BSP was built using the
32 bit toolchain. This takes advantage of the AArch32 mode of the Cortex-A53's -
the README describes how to switch to AArch32 mode through JTAG.

> 
> --
> *Mathew Benson*
> CEO | Chief Engineer
> Windhover Labs, LLC
> 832-640-4018
> 
> 
> www.windhoverlabs.com
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Sincerely,
Jeff Kubascik