RISC-V double float alignment

[Jiri Gaisler]

Hello,

As far as I understand, RISC-V does not require any particular alignment
of data structures in memory. Nevertheless, the compiler automatically
aligns data structures on their natural sizes, i.e. ints are aligned on
4-byte and doubles on 8-bytes boundaries. sis-riscv with support for
doubles (extension D) checks that load and store double are properly
aligned on 8-byte boundaries. This works fine for all compiler-generated
code, (e.g. paranoia) but fails for spcontext01, where the context save
function in riscv-exception-handler.S tries to save 64-bit floating
point registers on a non-aligned stack address.

Is this an oversight in the code, or does the hardware (and simulators)
have to support unaligned accesses?

Jiri.