RISC-V double float alignment

[Chris Johns]

On 2/2/19 6:53 am, Joel Sherrill wrote:
> Then we should ensure proper alignment since we NEVER want an unaligned
> exception on any architecture if it is avoidable. No point in taking the likely
> performance hit or exception. 

Is this documented anywhere?

It is an important issue because a performance hit such as unaligned accesses
silently happening is difficult to see and it tends to be accounted for as RTEMS
not performing or hardware not performing. Is this something we could test for
and check?

I personally have never stopped and checked a BSP for correct alignment in all
cases or the critical cases before using and when something exposes it I have
been surprised.

Chris