RISC-V double float alignment
joel at rtems.org
Mon Feb 4 23:56:56 UTC 2019
On Mon, Feb 4, 2019 at 5:07 PM Chris Johns <chrisj at rtems.org> wrote:
> On 2/2/19 6:53 am, Joel Sherrill wrote:
> > Then we should ensure proper alignment since we NEVER want an unaligned
> > exception on any architecture if it is avoidable. No point in taking the
> > performance hit or exception.
> Is this documented anywhere?
Unless it is in the porting guide, I doubt it. Alignment issues for
and the stack is a porting issue.
I was just thinking of the m68k where it allowed unaligned accesses but
was often a hidden performance penalty.
> It is an important issue because a performance hit such as unaligned
> silently happening is difficult to see and it tends to be accounted for as
> not performing or hardware not performing. Is this something we could test
> and check?
I don't know if it could be a static assertion but it could be a debug
It could certainly be checked with a normal test which peeked under the
> I personally have never stopped and checked a BSP for correct alignment in
> cases or the critical cases before using and when something exposes it I
> been surprised.
Me too. We all assume that alignment was thought through by the person who
did the port. Similar to finding caching disabled on a BSP.
I suppose if we identify the critical structures that a test could check
But we should be careful about this. What is minimum needed and what is
for performance? 4 or 8 byte alignments would avoid faults/unaligned
16 or 32 byte would be performance helps on many architectures for larger
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