SMP Testing of RISC-V

[Sebastian Huber]

On 20/05/2019 20:23, Joel Sherrill wrote:
> Hi
>
> I can't seem to find the number of cores the RISC-V port has been tested
> on. I couldn't even find test results for riscv RTEMS in the archives. 
> Info
> appreciated.

I tested with up to two cores and mostly using a 64-bit target. It 
should work on up to 32 cores.

>
> I see rtems-tester configurations for spike and sis. Are there any for 
> qemu?
> I thought qemu worked for RISC-V even if it had to be a special version.

The configurations without the _spike use Qemu.

-- 
Sebastian Huber, embedded brains GmbH

Address : Dornierstr. 4, D-82178 Puchheim, Germany
Phone   : +49 89 189 47 41-16
Fax     : +49 89 189 47 41-09
E-Mail  : sebastian.huber at embedded-brains.de
PGP     : Public key available on request.

Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.