SMP Testing of RISC-V
sebastian.huber at embedded-brains.de
Tue May 21 04:23:27 UTC 2019
On 20/05/2019 20:23, Joel Sherrill wrote:
> I can't seem to find the number of cores the RISC-V port has been tested
> on. I couldn't even find test results for riscv RTEMS in the archives.
I tested with up to two cores and mostly using a 64-bit target. It
should work on up to 32 cores.
> I see rtems-tester configurations for spike and sis. Are there any for
> I thought qemu worked for RISC-V even if it had to be a special version.
The configurations without the _spike use Qemu.
Sebastian Huber, embedded brains GmbH
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