SMP Testing of RISC-V
joel at rtems.org
Tue May 21 14:26:18 UTC 2019
On Mon, May 20, 2019 at 11:23 PM Sebastian Huber <
sebastian.huber at embedded-brains.de> wrote:
> On 20/05/2019 20:23, Joel Sherrill wrote:
> > Hi
> > I can't seem to find the number of cores the RISC-V port has been tested
> > on. I couldn't even find test results for riscv RTEMS in the archives.
> > Info
> > appreciated.
> I tested with up to two cores and mostly using a 64-bit target. It
> should work on up to 32 cores.
Was this on hardware or qemu?
> > I see rtems-tester configurations for spike and sis. Are there any for
> > qemu?
> > I thought qemu worked for RISC-V even if it had to be a special version.
> The configurations without the _spike use Qemu.
Thanks. Is this one of the RSB qemu configurations?
I am trying to figure out which BSP variants are expected to work with
which simulators and in what configurations so I can add them to the
semi-automated test sweep script I have been trying to run once a week.
Spike in the RSB doesn't build for me.
So I haven't found a combination of BSP and simulator to add.
> Sebastian Huber, embedded brains GmbH
> Address : Dornierstr. 4, D-82178 Puchheim, Germany
> Phone : +49 89 189 47 41-16
> Fax : +49 89 189 47 41-09
> E-Mail : sebastian.huber at embedded-brains.de
> PGP : Public key available on request.
> Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.
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