[PATCH v4] riscv: add freedom E310 Arty A7 bsp

[Sebastian Huber]

On 11/10/2019 08:18, Pragnesh Patel wrote:
>>>   RISCV_LINKCMD([RISCV_RAM_REGION_BEGIN],[begin of the RAM region for linker command file (default is 0x70000000 for 64-bit with -mcmodel=medlow and 0x80000000 for all other)],[${RISCV_RAM_REGION_BEGIN_DEFAULT}])
>>> -RISCV_LINKCMD([RISCV_RAM_REGION_SIZE],[size of the RAM region for linker command file (default 64MiB)],[0x04000000])
>>> +RISCV_LINKCMD([RISCV_RAM_REGION_SIZE],[size of the RAM region for linker command file (default is 256 MiB for frdme310arty and 64 MiB for all other)],[${RISCV_RAM_REGION_SIZE_DEFAULT}])
>>>
>> No need for this change?
> Arty A7 100T has a 256 MB of RAM. So,  do you want me to make
> RISCV_RAM_REGION_SIZE to default 64 MB for frdme310arty?

Since we have now a BSP variant for this board I think it makes sense to 
have all RAM available by default.

-- 
Sebastian Huber, embedded brains GmbH

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