[PATCH v3] riscv: add freedom E310 Arty A7 bsp
Pragnesh Patel
pragnesh.patel at sifive.com
Fri Sep 27 11:20:10 UTC 2019
Added support for Sifive Freedom FE310 soc on Arty A7 FPGA board.
Update #3785.
Signed-off-by: Pragnesh Patel <pragnesh.patel at sifive.com>
---
Changes in v3:
- Remove bsps/riscv/frdme310arty/ directory and added support for
Freedom FE310 soc in common bsps/riscv/riscv/ directory
- Added #define RISCV_ENABLE_FRDME310ARTY_SUPPORT in configure.ac
to enable support for FE310
- Change the RISCV_RAM_REGION_SIZE to 256 MB for riscv
Changes in v2:
bsps/riscv/frdme310arty/btimer/btimer.c
- Remove the read_csr() function from btimer.c
- Remove CONFIG_BTIMER_RISCV_GET_MCYCLES macro to get time in
microseconds
bsps/riscv/frdme310arty/clock/clockdrv.c
bsps/riscv/riscv/clock/clockdrv.c
- Delete both files and Add bsps/riscv/shared/clock/clockdrv.c
- riscv_clock_get_timebase_frequency(): Get timebase-frequency from
cpus or cpu at 0 devicetree node because riscv uses "cpus" node and
frdme310arty uses "cpu at 0" node to look for timebase-frequency
- Remove rtems_counter_initialize_converter() and
rtems_timecounter_simple_install() functions
bsps/riscv/frdme310arty/include/bsp/riscv.h
- Remove unused frdme310arty_l2c_base;
bsps/riscv/frdme310arty/start/bsp_fatal_halt.c
bsps/riscv/riscv/start/bsp_fatal_halt.c
- Delete this file and Add bsps/riscv/shared/start/bsp_fatal_halt.c
bsps/riscv/frdme310arty/start/bspstart.c
- Remove unused function riscv_get_node_byname()
bsps/riscv/frdme310arty/start/linkcmds.in
- Use @RISCV_RAM_REGION_BEGIN@ and @RISCV_RAM_REGION_SIZE@ instead of
hard coded values
c/src/lib/libbsp/riscv/frdme310arty/Makefile.am
- librtemsbsp_a_SOURCES -> bsps/riscv/shared/start/bsp_fatal_halt.c
- librtemsbsp_a_SOURCES -> bsps/riscv/shared/clock/clockdrv.c
c/src/lib/libbsp/riscv/frdme310arty/configure.ac
- change RISCV_RAM_REGION_SIZE to default 256MiB
bsps/riscv/riscv/irq/irq.c
- Delete this irq.c and it will now use bsps/riscv/shared/irq/irq.c
c/src/lib/libbsp/riscv/riscv/Makefile.am
- librtemsbsp_a_SOURCES -> bsps/riscv/shared/start/bsp_fatal_halt.c
- librtemsbsp_a_SOURCES -> bsps/riscv/shared/clock/clockdrv.c
- librtemsbsp_a_SOURCES -> bsps/riscv/shared/irq/irq.c
bsps/include/bsp/fatal.h | 3 +-
bsps/riscv/riscv/clock/clockdrv.c | 16 ++--
bsps/riscv/riscv/console/console-config.c | 57 +++++++++++++
bsps/riscv/riscv/console/fe310-uart.c | 100 +++++++++++++++++++++++
bsps/riscv/riscv/dts/frdme310arty.dts | 130 ++++++++++++++++++++++++++++++
bsps/riscv/riscv/include/bsp/fe310-uart.h | 42 ++++++++++
bsps/riscv/riscv/include/bsp/riscv.h | 4 +
bsps/riscv/riscv/start/bspstart.c | 52 ++++++++++++
c/src/lib/libbsp/riscv/riscv/Makefile.am | 8 ++
c/src/lib/libbsp/riscv/riscv/configure.ac | 7 +-
10 files changed, 411 insertions(+), 8 deletions(-)
create mode 100644 bsps/riscv/riscv/console/fe310-uart.c
create mode 100644 bsps/riscv/riscv/dts/frdme310arty.dts
create mode 100644 bsps/riscv/riscv/include/bsp/fe310-uart.h
diff --git a/bsps/include/bsp/fatal.h b/bsps/include/bsp/fatal.h
index fae5461..3f8e1eb 100644
--- a/bsps/include/bsp/fatal.h
+++ b/bsps/include/bsp/fatal.h
@@ -152,7 +152,8 @@ typedef enum {
RISCV_FATAL_INVALID_PLIC_NDEV_IN_DEVICE_TREE,
RISCV_FATAL_TOO_LARGE_PLIC_NDEV_IN_DEVICE_TREE,
RISCV_FATAL_INVALID_INTERRUPT_AFFINITY,
- RISCV_FATAL_NO_NS16550_INTERRUPTS_IN_DEVICE_TREE
+ RISCV_FATAL_NO_NS16550_INTERRUPTS_IN_DEVICE_TREE,
+ RISCV_FATAL_NO_TLCLOCK_FREQUENCY_IN_DEVICE_TREE
} bsp_fatal_code;
RTEMS_NO_RETURN static inline void
diff --git a/bsps/riscv/riscv/clock/clockdrv.c b/bsps/riscv/riscv/clock/clockdrv.c
index 7e6034d..7f32dcf 100644
--- a/bsps/riscv/riscv/clock/clockdrv.c
+++ b/bsps/riscv/riscv/clock/clockdrv.c
@@ -130,15 +130,21 @@ static uint32_t riscv_clock_get_timecount(struct timecounter *base)
static uint32_t riscv_clock_get_timebase_frequency(const void *fdt)
{
int node;
- const uint32_t *val;
- int len;
+ fdt32_t *val;
+ int len=0;
node = fdt_path_offset(fdt, "/cpus");
- val = fdt_getprop(fdt, node, "timebase-frequency", &len);
+
+ val = (fdt32_t *) fdt_getprop(fdt, node, "timebase-frequency", &len);
+
if (val == NULL || len < 4) {
- bsp_fatal(RISCV_FATAL_NO_TIMEBASE_FREQUENCY_IN_DEVICE_TREE);
- }
+ int cpu0 = fdt_subnode_offset(fdt, node, "cpu at 0");
+ val = (fdt32_t *) fdt_getprop(fdt, cpu0, "timebase-frequency", &len);
+ if (val == NULL || len < 4) {
+ bsp_fatal(RISCV_FATAL_NO_TIMEBASE_FREQUENCY_IN_DEVICE_TREE);
+ }
+ }
return fdt32_to_cpu(*val);
}
diff --git a/bsps/riscv/riscv/console/console-config.c b/bsps/riscv/riscv/console/console-config.c
index 464b4b0..8a3472d 100644
--- a/bsps/riscv/riscv/console/console-config.c
+++ b/bsps/riscv/riscv/console/console-config.c
@@ -28,6 +28,11 @@
#include <libfdt.h>
#include <string.h>
+#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0
+#include <bsp/fe310-uart.h>
+fe310_uart_context driver_context;
+#endif
+
#if RISCV_ENABLE_HTIF_SUPPORT != 0
static htif_console_context htif_console_instance;
#endif
@@ -59,7 +64,18 @@ static int riscv_get_console_node(const void *fdt)
stdout_path = "";
}
+#if RISCV_ENABLE_FRDME310ARTY_SUPPORT > 0
+ int root;
+ int soc;
+ root = fdt_path_offset(fdt, "/");
+ soc = fdt_subnode_offset(fdt, root, "soc");
+
+ int offset=fdt_subnode_offset(fdt, soc,stdout_path);
+
+ return offset;
+#else
return fdt_path_offset(fdt, stdout_path);
+#endif
}
#if RISCV_CONSOLE_MAX_NS16550_DEVICES > 0
@@ -193,6 +209,27 @@ static void riscv_console_probe(void)
}
#endif
+#if RISCV_ENABLE_FRDME310ARTY_SUPPORT > 0
+ if (RISCV_CONSOLE_IS_COMPATIBLE(compat, compat_len, "sifive,uart0")) {
+ fe310_uart_context *ctx ;
+
+ ctx=&driver_context;
+ ctx->regs = (uintptr_t) riscv_fdt_get_address(fdt, node);
+ if (ctx->regs == 0)
+ {
+ bsp_fatal(RISCV_FATAL_NO_NS16550_REG_IN_DEVICE_TREE);
+ }
+
+ if (node == console_node) {
+ riscv_console.context = &ctx->base;
+ riscv_console.putchar = fe310_console_putchar;
+ riscv_console.getchar = fe310_uart_read;
+ }
+
+ rtems_termios_device_context_initialize(&ctx->base, "FE310UART");
+ }
+#endif
+
node = fdt_next_node(fdt, node, NULL);
}
@@ -224,6 +261,10 @@ rtems_status_code console_initialize(
size_t i;
#endif
+#if RISCV_ENABLE_FRDME310ARTY_SUPPORT > 0
+ char path[] = "/dev/ttyS0";
+#endif
+
rtems_termios_initialize();
#if RISCV_ENABLE_HTIF_SUPPORT != 0
@@ -255,6 +296,22 @@ rtems_status_code console_initialize(
}
#endif
+#if RISCV_ENABLE_FRDME310ARTY_SUPPORT > 0
+ fe310_uart_context * ctx = &driver_context;
+
+ rtems_termios_device_install(
+ path,
+ &fe310_uart_handler,
+ NULL,
+ &ctx->base
+ );
+
+ if (&ctx->base == riscv_console.context) {
+ link(path, CONSOLE_DEVICE_NAME);
+ }
+
+#endif
+
return RTEMS_SUCCESSFUL;
}
diff --git a/bsps/riscv/riscv/console/fe310-uart.c b/bsps/riscv/riscv/console/fe310-uart.c
new file mode 100644
index 0000000..06b312f
--- /dev/null
+++ b/bsps/riscv/riscv/console/fe310-uart.c
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2019 Sachin Ghadi <sachin.ghadi at sifive.com>
+ * Copyright (c) 2019 Pragnesh Patel <pragnesh.patel at sifive.com>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+
+#include <bsp/riscv.h>
+#include <bsp/fe310-uart.h>
+
+#include <assert.h>
+
+static void irq_handler(void *arg)
+{
+ /*TODO*/
+}
+
+int fe310_uart_read(rtems_termios_device_context *base)
+{
+ fe310_uart_context * ctx = (fe310_uart_context*) base;
+ size_t i;
+
+ if (((ctx->regs->rxdata) & TXRXREADY) != 0) {
+ return -1;
+ } else {
+ return ctx->regs->rxdata;
+ }
+}
+
+static ssize_t fe310_uart_write (
+ rtems_termios_device_context *base,
+ const char *buf,
+ size_t n
+)
+{
+ fe310_uart_context * ctx = (fe310_uart_context*) base;
+ size_t i;
+
+ rtems_status_code sc;
+
+ (ctx->regs)->div = riscv_get_core_frequency()/ 115200 - 1;
+ (ctx->regs)->txctrl |= 1;
+ (ctx->regs)->rxctrl |= 1;
+
+ for (i = 0; i < n; ++i) {
+ while (((ctx->regs->txdata) & TXRXREADY) != 0) {
+ ;
+ }
+ ctx->regs->txdata = buf[i];
+ }
+ return n;
+}
+
+void fe310_console_putchar(rtems_termios_device_context * context,char c)
+{
+ fe310_uart_write ( context, &c,1);
+}
+
+void console_context_init(
+ rtems_termios_device_context *base,
+ int device_tree_node
+)
+{
+ /*TODO*/
+}
+
+static bool fe310_uart_first_open (
+ rtems_termios_tty *tty,
+ rtems_termios_device_context *base,
+ struct termios *term,
+ rtems_libio_open_close_args_t *args
+)
+{
+ fe310_uart_context * ctx;
+ rtems_status_code sc;
+
+ /* Configure GPIO to be UART */
+
+ sc = rtems_termios_set_initial_baud (tty, B115200);
+ if ( sc != RTEMS_SUCCESSFUL ) {
+ return false;
+ }
+
+ /* Set up a baud rate and enable tx and rx */
+ ctx = (fe310_uart_context *) base;
+ (ctx->regs)->div = riscv_get_core_frequency()/ 115200 - 1;
+ (ctx->regs)->txctrl |= 1;
+ (ctx->regs)->rxctrl |= 1;
+ return true;
+};
+
+const rtems_termios_device_handler fe310_uart_handler = {
+ .first_open = fe310_uart_first_open,
+ .write = fe310_uart_write,
+ .poll_read = fe310_uart_read,
+ .mode = TERMIOS_POLLED
+};
diff --git a/bsps/riscv/riscv/dts/frdme310arty.dts b/bsps/riscv/riscv/dts/frdme310arty.dts
new file mode 100644
index 0000000..a7a216d
--- /dev/null
+++ b/bsps/riscv/riscv/dts/frdme310arty.dts
@@ -0,0 +1,130 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "SiFive,FE310G-dev", "fe310-dev", "sifive-dev";
+ model = "SiFive,FE310G";
+ L20: chosen {
+ stdout-path = "serial at 20000000";
+ };
+ L17: cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ L6: cpu at 0 {
+ clocks = <&refclk>;
+ compatible = "sifive,rocket0", "riscv";
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <16384>;
+ next-level-cache = <&L12>;
+ reg = <0>;
+ riscv,isa = "rv32imac";
+ sifive,dtim = <&L5>;
+ sifive,itim = <&L4>;
+ status = "okay";
+ timebase-frequency = <1000000>;
+ L3: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ };
+ L16: soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "SiFive,FE310G-soc", "fe310-soc", "sifive-soc", "simple-bus";
+ ranges;
+ L19: tlclk {
+ #clock-cells = <0>;
+ clock-frequency = <32500000>;
+ clock-output-names = "tlclk";
+ compatible = "fixed-clock";
+ };
+ refclk: refclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <66666666>;
+ clock-output-names = "refclk";
+ };
+ L1: clint at 2000000 {
+ compatible = "riscv,clint0";
+ interrupts-extended = <&L3 3 &L3 7>;
+ reg = <0x2000000 0x10000>;
+ reg-names = "control";
+ };
+ L2: debug-controller at 0 {
+ compatible = "sifive,debug-013", "riscv,debug-013";
+ interrupts-extended = <&L3 65535>;
+ reg = <0x0 0x1000>;
+ reg-names = "control";
+ };
+ L5: dtim at 80000000 {
+ compatible = "sifive,dtim0";
+ reg = <0x80000000 0x10000>;
+ reg-names = "mem";
+ };
+ L8: error-device at 3000 {
+ compatible = "sifive,error0";
+ reg = <0x3000 0x1000>;
+ reg-names = "mem";
+ };
+ L9: global-external-interrupts {
+ interrupt-parent = <&L0>;
+ interrupts = <1 2 3 4>;
+ };
+ L13: gpio at 20002000 {
+ compatible = "sifive,gpio0";
+ interrupt-parent = <&L0>;
+ interrupts = <7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22>;
+ reg = <0x20002000 0x1000>;
+ reg-names = "control";
+ };
+ L0: interrupt-controller at c000000 {
+ #interrupt-cells = <1>;
+ compatible = "riscv,plic0";
+ interrupt-controller;
+ interrupts-extended = <&L3 11>;
+ reg = <0xc000000 0x4000000>;
+ reg-names = "control";
+ riscv,max-priority = <7>;
+ riscv,ndev = <26>;
+ };
+ L4: itim at 8000000 {
+ compatible = "sifive,itim0";
+ reg = <0x8000000 0x4000>;
+ reg-names = "mem";
+ };
+ L10: local-external-interrupts-0 {
+ interrupt-parent = <&L3>;
+ interrupts = <16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31>;
+ };
+ L14: pwm at 20005000 {
+ compatible = "sifive,pwm0";
+ interrupt-parent = <&L0>;
+ interrupts = <23 24 25 26>;
+ reg = <0x20005000 0x1000>;
+ reg-names = "control";
+ };
+ L11: serial at 20000000 {
+ compatible = "sifive,uart0";
+ interrupt-parent = <&L0>;
+ interrupts = <5>;
+ reg = <0x20000000 0x1000>;
+ reg-names = "control";
+ };
+ L12: spi at 20004000 {
+ compatible = "sifive,spi0";
+ interrupt-parent = <&L0>;
+ interrupts = <6>;
+ reg = <0x20004000 0x1000 0x40000000 0x20000000>;
+ reg-names = "control", "mem";
+ };
+ L7: teststatus at 4000 {
+ compatible = "sifive,test0";
+ reg = <0x4000 0x1000>;
+ };
+ };
+};
diff --git a/bsps/riscv/riscv/include/bsp/fe310-uart.h b/bsps/riscv/riscv/include/bsp/fe310-uart.h
new file mode 100644
index 0000000..065e12a
--- /dev/null
+++ b/bsps/riscv/riscv/include/bsp/fe310-uart.h
@@ -0,0 +1,42 @@
+ /*
+ * Copyright (c) 2019 Sachin Ghadi <sachin.ghadi at sifive.com>
+ * Copyright (c) 2019 Pragnesh Patel <pragnesh.patel at sifive.com>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef FE310_UART_H
+#define FE310_UART_H
+
+#define TXRXREADY (1 << 31)
+
+#include <rtems/termiostypes.h>
+#include <rtems/irq.h>
+
+typedef struct {
+ uint32_t txdata;
+ uint32_t rxdata;
+ uint32_t txctrl;
+ uint32_t rxctrl;
+ uint32_t ie;
+ uint32_t ip;
+ uint32_t div;
+} fe310_uart_t;
+
+/* Low-level driver specific data structure */
+typedef struct {
+ rtems_termios_device_context base;
+ const char *device_name;
+ volatile fe310_uart_t *regs;
+} fe310_uart_context;
+
+int fe310_uart_read(rtems_termios_device_context *base);
+void fe310_console_putchar(rtems_termios_device_context * context,char c);
+
+extern const rtems_termios_device_handler fe310_uart_handler;
+
+extern fe310_uart_context driver_context;
+
+#endif /* FE310_UART_H */
diff --git a/bsps/riscv/riscv/include/bsp/riscv.h b/bsps/riscv/riscv/include/bsp/riscv.h
index 374d5f7..f2f1a59 100644
--- a/bsps/riscv/riscv/include/bsp/riscv.h
+++ b/bsps/riscv/riscv/include/bsp/riscv.h
@@ -38,6 +38,10 @@ extern volatile RISCV_CLINT_regs *riscv_clint;
void *riscv_fdt_get_address(const void *fdt, int node);
+#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0
+uint32_t riscv_get_core_frequency(void);
+#endif
+
#ifdef RTEMS_SMP
extern uint32_t riscv_hart_count;
#else
diff --git a/bsps/riscv/riscv/start/bspstart.c b/bsps/riscv/riscv/start/bspstart.c
index d4c4e1f..b3b33b5 100644
--- a/bsps/riscv/riscv/start/bspstart.c
+++ b/bsps/riscv/riscv/start/bspstart.c
@@ -30,6 +30,11 @@
#include <bsp/riscv.h>
#include <libfdt.h>
+#include <string.h>
+
+#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0
+unsigned int riscv_core_freq;
+#endif
void *riscv_fdt_get_address(const void *fdt, int node)
{
@@ -161,8 +166,55 @@ uint32_t riscv_get_hart_index_by_phandle(uint32_t phandle)
return UINT32_MAX;
}
+#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0
+static uint32_t get_core_frequency(void)
+{
+ uint32_t node;
+ const char *fdt=bsp_fdt_get();
+
+ char *tlclk;
+ uint32_t len;
+
+ do
+ {
+ node=fdt_node_offset_by_compatible(fdt, -1,"fixed-clock");
+ uint32_t *val=NULL;
+ if(node>0)
+ {
+ tlclk = fdt_getprop(fdt, node, "clock-output-names", &len);
+
+ if (strcmp(tlclk,"tlclk") == 0)
+ {
+ val = fdt_getprop(fdt, node, "clock-frequency", &len);
+ if(val !=NULL)
+ {
+ riscv_core_freq=fdt32_to_cpu(*val);
+ break;
+ }
+ }
+ }else
+ {
+ bsp_fatal(RISCV_FATAL_NO_TLCLOCK_FREQUENCY_IN_DEVICE_TREE);
+ }
+
+ } while (node > 0);
+
+ return riscv_core_freq;
+}
+
+inline uint32_t riscv_get_core_frequency(void)
+{
+ return riscv_core_freq;
+}
+#endif
+
void bsp_start(void)
{
riscv_find_harts();
bsp_interrupt_initialize();
+
+#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0
+ riscv_core_freq=get_core_frequency();
+#endif
+
}
diff --git a/c/src/lib/libbsp/riscv/riscv/Makefile.am b/c/src/lib/libbsp/riscv/riscv/Makefile.am
index 34bedf8..15b0865 100644
--- a/c/src/lib/libbsp/riscv/riscv/Makefile.am
+++ b/c/src/lib/libbsp/riscv/riscv/Makefile.am
@@ -46,7 +46,11 @@ librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/start/bspgetworkarea-defa
librtemsbsp_a_SOURCES +=../../../../../../bsps/riscv/riscv/clock/clockdrv.c
# Timer
+#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0
+librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/btimer/btimer-cpucounter.c
+#else
librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/btimer/btimer-stub.c
+#endif
# IRQ
librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-default-handler.c
@@ -60,6 +64,10 @@ librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/serial/console-termio
librtemsbsp_a_SOURCES += ../../../../../../bsps/riscv/riscv/console/console-config.c
librtemsbsp_a_SOURCES += ../../../../../../bsps/riscv/riscv/console/htif.c
+#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0
+librtemsbsp_a_SOURCES += ../../../../../../bsps/riscv/riscv/console/fe310-uart.c
+#endif
+
if HAS_SMP
librtemsbsp_a_SOURCES += ../../../../../../bsps/riscv/riscv/start/bspsmp.c
endif
diff --git a/c/src/lib/libbsp/riscv/riscv/configure.ac b/c/src/lib/libbsp/riscv/riscv/configure.ac
index b01dee2..e6473ccd 100644
--- a/c/src/lib/libbsp/riscv/riscv/configure.ac
+++ b/c/src/lib/libbsp/riscv/riscv/configure.ac
@@ -36,9 +36,12 @@ RTEMS_BSPOPTS_HELP([RISCV_MAXIMUM_EXTERNAL_INTERRUPTS],[maximum number of extern
RTEMS_BSPOPTS_SET([RISCV_ENABLE_HTIF_SUPPORT],[*],[])
RTEMS_BSPOPTS_HELP([RISCV_ENABLE_HTIF_SUPPORT],[enables the HTIF support if defined to a non-zero value, otherwise it is disabled (disabled by default)])
-RTEMS_BSPOPTS_SET([RISCV_CONSOLE_MAX_NS16550_DEVICES],[*],[2])
+RTEMS_BSPOPTS_SET([RISCV_CONSOLE_MAX_NS16550_DEVICES],[*],[])
RTEMS_BSPOPTS_HELP([RISCV_CONSOLE_MAX_NS16550_DEVICES],[maximum number of NS16550 devices supported by the console driver (2 by default)])
+RTEMS_BSPOPTS_SET([RISCV_ENABLE_FRDME310ARTY_SUPPORT],[*],[1])
+RTEMS_BSPOPTS_HELP([RISCV_ENABLE_FRDME310ARTY_SUPPORT],[enables support sifive Freedom E310 Arty board if defined to a non-zero value,otherwise it is disabled (disabled by default)])
+
RTEMS_BSP_CLEANUP_OPTIONS
case "${RTEMS_BSP}" in
@@ -59,7 +62,7 @@ AC_ARG_VAR([$1],[$2])dnl
])
RISCV_LINKCMD([RISCV_RAM_REGION_BEGIN],[begin of the RAM region for linker command file (default is 0x70000000 for 64-bit with -mcmodel=medlow and 0x80000000 for all other)],[${RISCV_RAM_REGION_BEGIN_DEFAULT}])
-RISCV_LINKCMD([RISCV_RAM_REGION_SIZE],[size of the RAM region for linker command file (default 64MiB)],[0x04000000])
+RISCV_LINKCMD([RISCV_RAM_REGION_SIZE],[size of the RAM region for linker command file (default 256MiB)],[0x10000000])
AC_CONFIG_FILES([
Makefile
--
2.7.4
More information about the devel
mailing list