[PATCH 2/2] bsps: Fix GICv3 arm_gic_trigger_sgi()

[Kinsey Moore]

-----Original Message-----
From: devel <devel-bounces at rtems.org> On Behalf Of Sebastian Huber
Sent: Wednesday, December 9, 2020 07:35
To: devel at rtems.org
Subject: [PATCH 2/2] bsps: Fix GICv3 arm_gic_trigger_sgi()

Use the targets parameter to determine the targets of the SGI.

Update #4202.
---
 bsps/shared/dev/irq/arm-gicv3.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/bsps/shared/dev/irq/arm-gicv3.c b/bsps/shared/dev/irq/arm-gicv3.c index db10371c72..569c7610c4 100644
--- a/bsps/shared/dev/irq/arm-gicv3.c
+++ b/bsps/shared/dev/irq/arm-gicv3.c
@@ -356,7 +356,7 @@ void arm_gic_trigger_sgi(
   uint64_t value = ICC_SGIR_AFFINITY2(MPIDR_AFFINITY2_GET(mpidr))
                  | ICC_SGIR_INTID(vector)
                  | ICC_SGIR_AFFINITY1(MPIDR_AFFINITY1_GET(mpidr))
-                 | ICC_SGIR_CPU_TARGET_LIST(1);
+                 | ICC_SGIR_CPU_TARGET_LIST(targets);

Does the tm27 test still function on the Cortex-R52 or the generic A53 BSP after this change? The GICv2 implementation uses the filter to decide which CPU to send to since the target is set to 0 for that test. I don't see a defined behavior in the documentation for GICv3 of an all-zero target list since the filter isn't being taken into account here.

Kinsey