[PATCH 2/2] bsps: Remove gicvx_interrupt_dispatch()

[Sebastian Huber]

Avoid one level of indirection.

Update #4202.
---
 bsps/aarch64/shared/irq/irq-arm-gicvx-aarch64.c | 5 -----
 bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c     | 5 -----
 bsps/include/dev/irq/arm-gic-irq.h              | 6 ------
 bsps/shared/dev/irq/arm-gicv2.c                 | 2 +-
 bsps/shared/dev/irq/arm-gicv3.c                 | 2 +-
 5 files changed, 2 insertions(+), 18 deletions(-)

diff --git a/bsps/aarch64/shared/irq/irq-arm-gicvx-aarch64.c b/bsps/aarch64/shared/irq/irq-arm-gicvx-aarch64.c
index 67839118e1..5caf717bf1 100644
--- a/bsps/aarch64/shared/irq/irq-arm-gicvx-aarch64.c
+++ b/bsps/aarch64/shared/irq/irq-arm-gicvx-aarch64.c
@@ -57,8 +57,3 @@ void arm_interrupt_facility_set_exception_handler(void)
     _AArch64_Exception_interrupt_nest
   );
 }
-
-void bsp_interrupt_dispatch(void)
-{
-  gicvx_interrupt_dispatch();
-}
diff --git a/bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c b/bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c
index b9267aecba..7c0462d04d 100644
--- a/bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c
+++ b/bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c
@@ -54,8 +54,3 @@ void arm_interrupt_facility_set_exception_handler(void)
     _ARMV4_Exception_interrupt
   );
 }
-
-void bsp_interrupt_dispatch(void)
-{
-  gicvx_interrupt_dispatch();
-}
diff --git a/bsps/include/dev/irq/arm-gic-irq.h b/bsps/include/dev/irq/arm-gic-irq.h
index d4b197bbb7..5270331624 100644
--- a/bsps/include/dev/irq/arm-gic-irq.h
+++ b/bsps/include/dev/irq/arm-gic-irq.h
@@ -110,12 +110,6 @@ void arm_interrupt_facility_set_exception_handler(void);
  */
 void arm_interrupt_handler_dispatch(rtems_vector_number vector);
 
-/**
- * This is the GICv1/GICv2/GICv3 interrupt dispatcher that is to be called from the
- * architecture-specific implementation of the IRQ handler.
- */
-void gicvx_interrupt_dispatch(void);
-
 uint32_t arm_gic_irq_processor_count(void);
 
 void arm_gic_irq_initialize_secondary_cpu(void);
diff --git a/bsps/shared/dev/irq/arm-gicv2.c b/bsps/shared/dev/irq/arm-gicv2.c
index 97f397dffd..74989a4de5 100644
--- a/bsps/shared/dev/irq/arm-gicv2.c
+++ b/bsps/shared/dev/irq/arm-gicv2.c
@@ -49,7 +49,7 @@
 #define CPUIF_ICCICR GIC_CPUIF_ICCICR_ENABLE
 #endif
 
-void gicvx_interrupt_dispatch(void)
+void bsp_interrupt_dispatch(void)
 {
   volatile gic_cpuif *cpuif = GIC_CPUIF;
   uint32_t icciar = cpuif->icciar;
diff --git a/bsps/shared/dev/irq/arm-gicv3.c b/bsps/shared/dev/irq/arm-gicv3.c
index a7170006b6..c024e58df3 100644
--- a/bsps/shared/dev/irq/arm-gicv3.c
+++ b/bsps/shared/dev/irq/arm-gicv3.c
@@ -143,7 +143,7 @@ static volatile gic_sgi_ppi *gicv3_get_sgi_ppi(uint32_t cpu_index)
     (BSP_ARM_GIC_REDIST_BASE + cpu_index * 0x20000 + 0x10000);
 }
 
-void gicvx_interrupt_dispatch(void)
+void bsp_interrupt_dispatch(void)
 {
   uint32_t icciar = READ_SR(ICC_IAR1);
   rtems_vector_number vector = GIC_CPUIF_ICCIAR_ACKINTID_GET(icciar);
-- 
2.26.2