[PATCH] bsps/arm: Initialize priorities of PPIs

[Sebastian Huber]

From: "sebastian.huber" <sebastian.huber at ad346e48-6743-2946-b04c-964484d2d4e6>

At least on GICv1 the interrupts 0 up to including 31 are so called
Peripheral Private Interrupts (PPIs).  We have to initialize the
priority of the PPIs on secondary processors.
---
 bsps/arm/shared/irq/irq-gic.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/bsps/arm/shared/irq/irq-gic.c b/bsps/arm/shared/irq/irq-gic.c
index 7cf469d0f7..42ae6c4d7d 100644
--- a/bsps/arm/shared/irq/irq-gic.c
+++ b/bsps/arm/shared/irq/irq-gic.c
@@ -152,6 +152,7 @@ BSP_START_TEXT_SECTION void arm_gic_irq_initialize_secondary_cpu(void)
 {
   volatile gic_cpuif *cpuif = GIC_CPUIF;
   volatile gic_dist *dist = ARM_GIC_DIST;
+  uint32_t id;
 
   while ((dist->icddcr & GIC_DIST_ICDDCR_ENABLE) == 0) {
     /* Wait */
@@ -161,6 +162,11 @@ BSP_START_TEXT_SECTION void arm_gic_irq_initialize_secondary_cpu(void)
   dist->icdigr[0] = 0xffffffff;
 #endif
 
+  /* Initialize Peripheral Private Interrupts (PPIs) */
+  for (id = 0; id < 32; ++id) {
+    gic_id_set_priority(dist, id, PRIORITY_DEFAULT);
+  }
+
   cpuif->iccpmr = GIC_CPUIF_ICCPMR_PRIORITY(0xff);
   cpuif->iccbpr = GIC_CPUIF_ICCBPR_BINARY_POINT(0x0);
   cpuif->iccicr = CPUIF_ICCICR;
-- 
2.16.4