GSoC: Disabling interrupts while modifying translation table entries for armv7-A MMU.
utkarsh.rai60 at gmail.com
Sat Jul 18 04:10:31 UTC 2020
The translation table setting code has _ARM_Data_synchronization_barrier()
before and after invalidating the instruction and data TLB entry, this
ensures synchronization of instructions for the TLB invalidation in case of
multiple cores. My question is, do we have to explicitly disable interrupts
too while modifying the translation table entries? The ARM reference manual
is not very clear on this topic.
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