Cacheable OCM support for the Zynq BSP

[Jonathan Brandmeyer]

On Wed, Jun 10, 2020 at 5:57 PM Chris Johns <chrisj at rtems.org> wrote:

> On 11/6/20 9:30 am, Jonathan Brandmeyer wrote:
> > We've patched the RTEMS kernel in order to support using the Zynq
> on-chip memory
> > as inner-cacheable memory.  The enclosed patch should apply cleanly to
> master.
> >
> > Background: During normal startup, the ROM bootloader performs
> vendor-specific
> > initialization of  core 1, and then sits in a wait-for-event loop until a
> > special value has been written to a specific address in OCM.  In that
> state, the
> > MMU has not yet been initialized and core 1 is treating OCM as Device
> memory.
> >
> > By the time the RTEMS boot gets to _CPU_SMP_Start_processor, core 0's
> MMU has
> > already been initialized with the application-defined memory map.  I'd
> like to
> > use the on-chip memory as inner cacheable memory in my application.  In
> order to
> > ensure that the kick address write actually becomes visible to core 1, a
> cache
> > line flush of the affected line is necessary prior to sending the event
> that
> > wakes up the other core.
>
> Have the patches been tested with the OCM in the default state?
>

Yes.  Performing a cache flush by virtual address to a line which has
Device memory attributes appears to be harmless.

-- 
Jonathan Brandmeyer
PlanetiQ
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