Offset locations of registers in ARM context-switch code

[Sebastian Huber]

On 27/06/2020 19:02, Utkarsh Rai wrote:

> The 'Context_Control' structure in score/.../arm/cpu.h has registers 
> and attributes that need to be saved during context-switching.
> Some of these registers/attributes are conditionally compiled 
> depending upon the mode in which the processor is running. The 
> registers are saved by 'ldr' instruction by providing proper offset 
> form the context-control base address. These offsets are dependent on 
> the mode for which the compilation is done.
> For example, the 'is_executing' attribute has the following offset, 
> depending on various modes.
> ''
> #ifdef RTEMS_SMP
>   #if defined(ARM_MULTILIB_VFP)
>     #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 112
>   #elif defined(ARM_MULTILIB_HAS_THREAD_ID_REGISTER)
>     #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 48
>   #else
>     #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 44
>   #endif
> #endif ''
>
> My question is, what are the modes for which different registers in 
> the context control structure are compiled?
If you don't need new variants, then the defines you see in the header 
file are the relevant ones.