Need help to run a smp testsuite on erc32 with multi core

[Richi Dubey]

Hii,

I stumbled upon this problem again while trying to set up the
debugging environment. I have opened a small task ticket:
https://devel.rtems.org/ticket/3983#ticket.

On Wed, Apr 8, 2020 at 11:14 PM Gedare Bloom <gedare at rtems.org> wrote:
>
>
>
> On Wed, Apr 8, 2020, 11:17 AM Richi Dubey <richidubey at gmail.com> wrote:
>>
>> Dear Dr. Bloom,
>>
>> I understand. I would be more specific from next time.
>>
>> When I ran sis with no multi-core option, the result came out same as when I ran it with -m 2 option, (To simulate the executable with 2 cores). And on reading sis manual, I understood it didn't support erc32 multiprocessing, now I know the reason was because erc32 is a single core processor.
>>
>> I built erc32 on SPARC - RTEMS with --enable-smp option enabled.
>>
>> On trying to run the debugger, sparc-rtems5-gdb [file], It doesnt not support the command " tar sim -erc32" anymore(from https://devel.rtems.org/wiki/Debugging/sis) and I didn't know how to set a simulator as a target.
>
> This page is outdated. It needs to be reviewed, relevant info moved to docs, and page content replaced by a pointer to the docs.
>
> This should be added as a SmallTask ticket.
>
>>
>> Thank you.
>>
>> On Wed, Apr 8, 2020 at 1:03 AM Gedare Bloom <gedare at rtems.org> wrote:
>>>
>>> On Tue, Apr 7, 2020 at 1:30 PM Richi Dubey <richidubey at gmail.com> wrote:
>>> >
>>> > Hey everyone,
>>> >
>>> > Can someone please help me out with running a smp testsuite on erc32(which uses SPARC instruction set). I tried using sis, but the -m option for multi core doesnt seem to work, as the sis readme says: "-m cores : Enable the number of cores (2 - 4) in a leon3 or RISC-V multi-processor system." and that sis supports:
>>> >
>>> What do you mean it doesn't seem to work? What was broken/how do you
>>> know it was broken?
>>>
>>> How did you configure/build rtems?
>>>
>>> How did you invoke sis?
>>>
>>> What is the output of running sis?
>>>
>>> >  " sis is capable of emulating four different processor systems:
>>> >  ERC32 ERC32 SPARC V7 processor
>>> > LEON2 LEON2 SPARC V8 processor
>>> > LEON3 LEON3 SPARC V8 processor
>>> >  RISC-V RISC-V (RV32IMACFD) processor "
>>> >
>>> > So if sis does not support multi-core for erc32 systems, what should I use to run a smp program on erc32?
>>> >
>>> >
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