[PATCH rtems 9/9] bsp/imxrt: Add new BSP
Christian Mauderer
christian.mauderer at embedded-brains.de
Tue Nov 17 11:04:32 UTC 2020
Update #4180
---
bsps/arm/imxrt/console/console.c | 490 +++++++
bsps/arm/imxrt/dts/imxrt1050-evkb.c | 800 +++++++++++
bsps/arm/imxrt/dts/imxrt1050-evkb.dts | 410 ++++++
bsps/arm/imxrt/i2c/imxrt-lpi2c.c | 489 +++++++
bsps/arm/imxrt/include/bsp.h | 93 ++
bsps/arm/imxrt/include/bsp/flash-headers.h | 63 +
bsps/arm/imxrt/include/bsp/irq.h | 54 +
bsps/arm/imxrt/include/chip.h | 2 +
.../imxrt/include/imxrt/imxrt1050-pinfunc.h | 1236 +++++++++++++++++
bsps/arm/imxrt/include/imxrt/memory.h | 83 ++
bsps/arm/imxrt/include/tm27.h | 1 +
bsps/arm/imxrt/spi/imxrt-lpspi.c | 532 +++++++
bsps/arm/imxrt/start/bspstart.c | 141 ++
bsps/arm/imxrt/start/bspstarthooks.c | 133 ++
bsps/arm/imxrt/start/flash-boot-data.c | 37 +
bsps/arm/imxrt/start/flash-config.c | 60 +
bsps/arm/imxrt/start/flash-dcd.c | 38 +-
bsps/arm/imxrt/start/flash-ivt.c | 39 +
bsps/arm/imxrt/start/imxrt-ffec-init.c | 86 ++
bsps/arm/imxrt/start/linkcmds.flexspi | 35 +
bsps/arm/imxrt/start/linkcmds.sdram | 23 +
bsps/arm/shared/pins/imx_iomux.c | 5 +
bsps/include/bsp/fatal.h | 17 +-
spec/build/bsps/arm/imxrt/abi.yml | 20 +
spec/build/bsps/arm/imxrt/bspimxrt.yml | 248 ++++
spec/build/bsps/arm/imxrt/linkcmds.yml | 11 +
spec/build/bsps/arm/imxrt/linkcmdsmemory.yml | 67 +
spec/build/bsps/arm/imxrt/optlinkcmds.yml | 16 +
.../build/bsps/arm/imxrt/optmemflashcfgsz.yml | 19 +
.../build/bsps/arm/imxrt/optmemflashivtsz.yml | 18 +
spec/build/bsps/arm/imxrt/optmemflexspisz.yml | 17 +
spec/build/bsps/arm/imxrt/optmemnullsz.yml | 17 +
spec/build/bsps/arm/imxrt/optmemsdrambase.yml | 16 +
.../bsps/arm/imxrt/optmemsdramnocachesz.yml | 16 +
spec/build/bsps/arm/imxrt/optmemsdramsz.yml | 16 +
35 files changed, 5312 insertions(+), 36 deletions(-)
create mode 100644 bsps/arm/imxrt/console/console.c
create mode 100644 bsps/arm/imxrt/dts/imxrt1050-evkb.c
create mode 100644 bsps/arm/imxrt/dts/imxrt1050-evkb.dts
create mode 100644 bsps/arm/imxrt/i2c/imxrt-lpi2c.c
create mode 100644 bsps/arm/imxrt/include/bsp.h
create mode 100644 bsps/arm/imxrt/include/bsp/flash-headers.h
create mode 100644 bsps/arm/imxrt/include/bsp/irq.h
create mode 100644 bsps/arm/imxrt/include/chip.h
create mode 100644 bsps/arm/imxrt/include/imxrt/imxrt1050-pinfunc.h
create mode 100644 bsps/arm/imxrt/include/imxrt/memory.h
create mode 100644 bsps/arm/imxrt/include/tm27.h
create mode 100644 bsps/arm/imxrt/spi/imxrt-lpspi.c
create mode 100644 bsps/arm/imxrt/start/bspstart.c
create mode 100644 bsps/arm/imxrt/start/bspstarthooks.c
create mode 100644 bsps/arm/imxrt/start/flash-boot-data.c
create mode 100644 bsps/arm/imxrt/start/flash-config.c
create mode 100644 bsps/arm/imxrt/start/flash-ivt.c
create mode 100644 bsps/arm/imxrt/start/imxrt-ffec-init.c
create mode 100644 bsps/arm/imxrt/start/linkcmds.flexspi
create mode 100644 bsps/arm/imxrt/start/linkcmds.sdram
create mode 100644 spec/build/bsps/arm/imxrt/abi.yml
create mode 100644 spec/build/bsps/arm/imxrt/bspimxrt.yml
create mode 100644 spec/build/bsps/arm/imxrt/linkcmds.yml
create mode 100644 spec/build/bsps/arm/imxrt/linkcmdsmemory.yml
create mode 100644 spec/build/bsps/arm/imxrt/optlinkcmds.yml
create mode 100644 spec/build/bsps/arm/imxrt/optmemflashcfgsz.yml
create mode 100644 spec/build/bsps/arm/imxrt/optmemflashivtsz.yml
create mode 100644 spec/build/bsps/arm/imxrt/optmemflexspisz.yml
create mode 100644 spec/build/bsps/arm/imxrt/optmemnullsz.yml
create mode 100644 spec/build/bsps/arm/imxrt/optmemsdrambase.yml
create mode 100644 spec/build/bsps/arm/imxrt/optmemsdramnocachesz.yml
create mode 100644 spec/build/bsps/arm/imxrt/optmemsdramsz.yml
diff --git a/bsps/arm/imxrt/console/console.c b/bsps/arm/imxrt/console/console.c
new file mode 100644
index 0000000000..05320f2c4c
--- /dev/null
+++ b/bsps/arm/imxrt/console/console.c
@@ -0,0 +1,490 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <bsp.h>
+#include <bsp/fdt.h>
+#include <bsp/fatal.h>
+#include <bsp/irq.h>
+#include <rtems/bspIo.h>
+#include <rtems/console.h>
+#include <rtems/termiostypes.h>
+
+#include <inttypes.h>
+#include <libfdt.h>
+#include <stdio.h>
+
+#include <chip.h>
+#include <fsl_lpuart.h>
+
+#define LPUART_MAX_INSTANCES 8
+
+#define LPUART_DATA_RT (LPUART_DATA_R0T0_MASK | LPUART_DATA_R1T1_MASK | \
+ LPUART_DATA_R2T2_MASK | LPUART_DATA_R3T3_MASK | \
+ LPUART_DATA_R4T4_MASK | LPUART_DATA_R5T5_MASK | \
+ LPUART_DATA_R6T6_MASK | LPUART_DATA_R7T7_MASK | \
+ LPUART_DATA_R8T8_MASK | LPUART_DATA_R9T9_MASK)
+
+typedef struct {
+ rtems_termios_device_context base;
+ volatile LPUART_Type *regs;
+ rtems_vector_number irq;
+ const char *path;
+ uint32_t src_clock_hz;
+ lpuart_config_t config;
+} imxrt_lpuart_context;
+
+/* Static memory for the console UART because it might is initialized early. */
+static imxrt_lpuart_context imxrt_lpuart_console_instance;
+static imxrt_lpuart_context *imxrt_lpuart_console;
+
+static void imxrt_output_char(char c);
+static int imxrt_poll_char(void);
+
+static imxrt_lpuart_context *imxrt_lpuart_get_context(
+ rtems_termios_device_context *base
+)
+{
+ return RTEMS_CONTAINER_OF(base, imxrt_lpuart_context, base);
+}
+
+static void imxrt_lpuart_write_polled(
+ rtems_termios_device_context *base,
+ char c
+)
+{
+ imxrt_lpuart_context *ctx = imxrt_lpuart_get_context(base);
+ volatile LPUART_Type *regs = ctx->regs;
+ rtems_interrupt_level isr_cookie;
+ uint32_t ctrl;
+
+ rtems_interrupt_disable(isr_cookie);
+ ctrl = ctx->regs->CTRL;
+ ctx->regs->CTRL = ctrl & ~LPUART_CTRL_TIE_MASK;
+ rtems_interrupt_enable(isr_cookie);
+
+ while ((regs->STAT & LPUART_STAT_TDRE_MASK) == 0) {
+ /* Wait */
+ }
+
+ regs->DATA = c;
+
+ if ((ctrl & LPUART_CTRL_TIE_MASK) != 0) {
+ ctx->regs->CTRL |= LPUART_CTRL_TIE_MASK;
+ }
+}
+
+static int imxrt_lpuart_read_polled(rtems_termios_device_context *base)
+{
+ uint32_t data;
+ imxrt_lpuart_context *ctx = imxrt_lpuart_get_context(base);
+ volatile LPUART_Type *regs = ctx->regs;
+
+ data = regs->DATA;
+
+ if ( data & (LPUART_DATA_PARITYE_MASK | LPUART_DATA_FRETSC_MASK |
+ LPUART_DATA_RXEMPT_MASK) ) {
+ return -1;
+ } else {
+ return data & LPUART_DATA_RT;
+ }
+}
+
+static bool imxrt_lpuart_set_attributes(
+ rtems_termios_device_context *base,
+ const struct termios *term
+)
+{
+ imxrt_lpuart_context *ctx = imxrt_lpuart_get_context(base);
+
+ switch (term->c_cflag & CSIZE) {
+ case CS7:
+ ctx->config.dataBitsCount = kLPUART_SevenDataBits;
+ break;
+ case CS8:
+ ctx->config.dataBitsCount = kLPUART_EightDataBits;
+ break;
+ default:
+ return false;
+ break;
+ }
+
+ ctx->config.baudRate_Bps = rtems_termios_baud_to_number(term->c_ospeed);
+
+ if ((term->c_cflag & CSTOPB) != 0) {
+ ctx->config.stopBitCount = kLPUART_TwoStopBit;
+ } else {
+ ctx->config.stopBitCount = kLPUART_OneStopBit;
+ }
+
+ if ((term->c_cflag & PARENB) != 0) {
+ if ((term->c_cflag & PARODD) != 0) {
+ ctx->config.parityMode = kLPUART_ParityOdd;
+ } else {
+ ctx->config.parityMode = kLPUART_ParityEven;
+ }
+ } else {
+ ctx->config.parityMode = kLPUART_ParityDisabled;
+ }
+
+ if ((term->c_cflag & CREAD) != 0) {
+ ctx->config.enableRx = true;
+ } else {
+ ctx->config.enableRx = false;
+ }
+
+ if ((term->c_cflag & CCTS_OFLOW) != 0) {
+ ctx->config.enableTxCTS = true;
+ } else {
+ ctx->config.enableTxCTS = false;
+ }
+
+ if ((term->c_cflag & CRTS_IFLOW) != 0) {
+ ctx->config.enableRxRTS = true;
+ } else {
+ ctx->config.enableRxRTS = false;
+ }
+
+ (void) LPUART_Init((LPUART_Type *)ctx->regs, &ctx->config,
+ ctx->src_clock_hz, false);
+
+ return true;
+}
+
+static uint32_t imxrt_lpuart_get_src_freq(void)
+{
+ uint32_t freq;
+ uint32_t mux;
+ uint32_t divider;
+
+ mux = CLOCK_GetMux(kCLOCK_UartMux);
+ divider = 1;
+
+ switch (mux) {
+ case 0: /* pll3_sw_clk */
+ freq = CLOCK_GetFreq(kCLOCK_Usb1PllClk);
+ divider = 6;
+ break;
+ case 1: /* OSC */
+ freq = CLOCK_GetFreq(kCLOCK_OscClk);
+ break;
+ default:
+ freq = 0;
+ }
+
+ divider *= CLOCK_GetDiv(kCLOCK_UartDiv) + 1U;
+ freq /= divider;
+
+ return freq;
+}
+
+static void imxrt_lpuart_init_hardware(imxrt_lpuart_context *ctx)
+{
+ (void) LPUART_Init((LPUART_Type *)ctx->regs, &ctx->config,
+ ctx->src_clock_hz, true);
+}
+
+#ifdef BSP_CONSOLE_USE_INTERRUPTS
+static void imxrt_lpuart_interrupt(void *arg)
+{
+ rtems_termios_tty *tty = arg;
+ rtems_termios_device_context *base = rtems_termios_get_device_context(tty);
+ imxrt_lpuart_context *ctx = imxrt_lpuart_get_context(base);
+ uint32_t stat;
+ uint32_t data;
+
+ stat = ctx->regs->STAT;
+
+ if ((stat & LPUART_STAT_RDRF_MASK) != 0) {
+ do {
+ char c;
+ data = ctx->regs->DATA;
+
+ if ((data & (LPUART_DATA_PARITYE_MASK | LPUART_DATA_FRETSC_MASK |
+ LPUART_DATA_RXEMPT_MASK)) == 0) {
+ c = data & LPUART_DATA_RT;
+ rtems_termios_enqueue_raw_characters(tty, &c, 1);
+ }
+ } while ((data & LPUART_DATA_RXEMPT_MASK) == 0);
+ }
+
+ if ((ctx->regs->CTRL & LPUART_CTRL_TIE_MASK) != 0
+ && (stat & LPUART_STAT_TDRE_MASK) != 0) {
+ /* Note: This will call imxrt_lpuart_write */
+ rtems_termios_dequeue_characters(tty, 1);
+ }
+}
+#endif
+
+static bool imxrt_lpuart_first_open(
+ rtems_termios_tty *tty,
+ rtems_termios_device_context *base,
+ struct termios *term,
+ rtems_libio_open_close_args_t *args
+)
+{
+#ifdef BSP_CONSOLE_USE_INTERRUPTS
+ rtems_status_code sc;
+#endif
+ imxrt_lpuart_context *ctx = imxrt_lpuart_get_context(base);
+ rtems_termios_set_initial_baud(tty, BSP_CONSOLE_BAUD);
+
+#ifdef BSP_CONSOLE_USE_INTERRUPTS
+ sc = rtems_interrupt_handler_install(
+ ctx->irq,
+ "LPUART",
+ RTEMS_INTERRUPT_SHARED,
+ imxrt_lpuart_interrupt,
+ tty
+ );
+ if (sc != RTEMS_SUCCESSFUL) {
+ return false;
+ }
+#endif
+
+ imxrt_lpuart_init_hardware(ctx);
+
+#ifdef BSP_CONSOLE_USE_INTERRUPTS
+ ctx->regs->CTRL |= LPUART_CTRL_RIE_MASK;
+#endif
+
+ imxrt_lpuart_set_attributes(base, term);
+
+ return true;
+}
+
+static void imxrt_lpuart_last_close(
+ rtems_termios_tty *tty,
+ rtems_termios_device_context *base,
+ rtems_libio_open_close_args_t *args
+)
+{
+ imxrt_lpuart_context *ctx = imxrt_lpuart_get_context(base);
+
+ LPUART_Deinit((LPUART_Type *)ctx->regs);
+
+#ifdef BSP_CONSOLE_USE_INTERRUPTS
+ (void) rtems_interrupt_handler_remove(
+ ctx->irq,
+ imxrt_lpuart_interrupt,
+ tty
+ );
+#endif
+}
+
+static void imxrt_lpuart_write(
+ rtems_termios_device_context *base,
+ const char *buf,
+ size_t len
+)
+{
+#ifdef BSP_CONSOLE_USE_INTERRUPTS
+ imxrt_lpuart_context *ctx = imxrt_lpuart_get_context(base);
+
+ if (len > 0) {
+ ctx->regs->DATA = (uint8_t) buf[0];
+ ctx->regs->CTRL |= LPUART_CTRL_TIE_MASK;
+ } else {
+ ctx->regs->CTRL &= ~LPUART_CTRL_TIE_MASK;
+ }
+#else
+ size_t i;
+
+ for (i = 0; i < len; ++i) {
+ imxrt_lpuart_write_polled(base, buf[i]);
+ }
+#endif
+}
+
+static const rtems_termios_device_handler imxrt_lpuart_handler = {
+ .first_open = imxrt_lpuart_first_open,
+ .last_close = imxrt_lpuart_last_close,
+ .write = imxrt_lpuart_write,
+ .set_attributes = imxrt_lpuart_set_attributes,
+#ifdef BSP_CONSOLE_USE_INTERRUPTS
+ .mode = TERMIOS_IRQ_DRIVEN,
+#else
+ .poll_read = imxrt_lpuart_read_polled,
+ .mode = TERMIOS_POLLED,
+#endif
+};
+
+static int imxrt_lpuart_get_stdout_node(const void *fdt)
+{
+ int node;
+ const char *console;
+
+ node = fdt_path_offset(fdt, "/chosen");
+ if (node < 0) {
+ bsp_fatal(IMXRT_FATAL_NO_CONSOLE);
+ }
+
+ console = fdt_getprop(fdt, node, "stdout-path", NULL);
+ if (console == NULL) {
+ bsp_fatal(IMXRT_FATAL_NO_CONSOLE);
+ }
+
+ node = fdt_path_offset(fdt, console);
+ if (node < 0) {
+ bsp_fatal(IMXRT_FATAL_NO_CONSOLE);
+ }
+
+ return node;
+}
+
+static void imxrt_lpuart_init_context_from_fdt(
+ imxrt_lpuart_context *ctx,
+ const void *fdt,
+ int node
+)
+{
+ memset(&ctx->base, 0, sizeof(ctx->base));
+
+ ctx->regs = imx_get_reg_of_node(fdt, node);
+ if (ctx->regs == NULL) {
+ bsp_fatal(IMXRT_FATAL_LPUART_INVALID_FDT);
+ }
+
+ ctx->irq = imx_get_irq_of_node(fdt, node, 0);
+ if (ctx->irq == BSP_INTERRUPT_VECTOR_INVALID) {
+ bsp_fatal(IMXRT_FATAL_LPUART_INVALID_FDT);
+ }
+
+ ctx->path = fdt_getprop(fdt, node, "rtems,path", NULL);
+ if (ctx->path == NULL) {
+ bsp_fatal(IMXRT_FATAL_LPI2C_INVALID_FDT);
+ }
+
+ ctx->src_clock_hz = imxrt_lpuart_get_src_freq();
+
+ LPUART_GetDefaultConfig(&ctx->config);
+ ctx->config.enableTx = true;
+ ctx->config.enableRx = true;
+
+ rtems_termios_device_context_initialize(&ctx->base, "LPUART");
+}
+
+static void imxrt_lpuart_console_probe_early(void)
+{
+ int node;
+ const void *fdt;
+
+ imxrt_lpuart_console = NULL;
+
+ fdt = bsp_fdt_get();
+ node = imxrt_lpuart_get_stdout_node(fdt);
+ imxrt_lpuart_init_context_from_fdt(&imxrt_lpuart_console_instance, fdt, node);
+ (void) LPUART_Init(
+ (LPUART_Type *)imxrt_lpuart_console_instance.regs,
+ &imxrt_lpuart_console_instance.config,
+ imxrt_lpuart_console_instance.src_clock_hz,
+ true
+ );
+ imxrt_lpuart_console = &imxrt_lpuart_console_instance;
+
+ BSP_output_char = imxrt_output_char;
+ BSP_poll_char = imxrt_poll_char;
+}
+
+rtems_status_code console_initialize(
+ rtems_device_major_number major,
+ rtems_device_minor_number minor,
+ void *arg
+)
+{
+ const void *fdt;
+ int stdout_node;
+ int node;
+ rtems_status_code sc;
+
+ fdt = bsp_fdt_get();
+ stdout_node = imxrt_lpuart_get_stdout_node(fdt);
+ node = -1;
+
+ rtems_termios_initialize();
+
+ do {
+ node = fdt_node_offset_by_compatible(fdt, node, "nxp,imxrt-lpuart");
+
+ if (node >= 0 && imxrt_fdt_node_is_enabled(fdt, node)) {
+ imxrt_lpuart_context *ctx;
+
+ if (node != stdout_node) {
+ ctx = calloc(1, sizeof(imxrt_lpuart_context));
+ if (ctx == NULL) {
+ bsp_fatal(IMXRT_FATAL_LPUART_ALLOC_FAILED);
+ }
+
+ imxrt_lpuart_init_context_from_fdt(ctx, fdt, node);
+
+ } else {
+ ctx = imxrt_lpuart_console;
+ if (ctx == NULL) {
+ imxrt_lpuart_console_probe_early();
+ ctx = imxrt_lpuart_console;
+ }
+ }
+
+ sc = rtems_termios_device_install(
+ ctx->path,
+ &imxrt_lpuart_handler,
+ NULL,
+ &ctx->base
+ );
+ if (sc != RTEMS_SUCCESSFUL) {
+ bsp_fatal(IMXRT_FATAL_LPUART_INSTALL_FAILED);
+ }
+
+ if (node == stdout_node) {
+ link(ctx->path, CONSOLE_DEVICE_NAME);
+ }
+ }
+ } while (node >= 0);
+
+ return RTEMS_SUCCESSFUL;
+}
+
+static void imxrt_output_char(char c)
+{
+ if (imxrt_lpuart_console != NULL) {
+ imxrt_lpuart_write_polled(&imxrt_lpuart_console->base, c);
+ }
+}
+
+static int imxrt_poll_char(void)
+{
+ return imxrt_lpuart_read_polled(&imxrt_lpuart_console->base);
+}
+
+static void imxrt_output_char_init(char c)
+{
+ imxrt_lpuart_console_probe_early();
+ imxrt_output_char(c);
+}
+
+BSP_output_char_function_type BSP_output_char = imxrt_output_char_init;
+
+BSP_polling_getchar_function_type BSP_poll_char = NULL;
diff --git a/bsps/arm/imxrt/dts/imxrt1050-evkb.c b/bsps/arm/imxrt/dts/imxrt1050-evkb.c
new file mode 100644
index 0000000000..b97337b264
--- /dev/null
+++ b/bsps/arm/imxrt/dts/imxrt1050-evkb.c
@@ -0,0 +1,800 @@
+/*
+ * Declarations for C structure representing binary file imxrt_dtb
+ *
+ * WARNING: Automatically generated -- do not edit!
+ */
+
+#include <sys/types.h>
+
+const unsigned char imxrt_dtb[] = {
+ 0xd0, 0x0d, 0xfe, 0xed, 0x00, 0x00, 0x24, 0xeb, 0x00, 0x00, 0x00, 0x38,
+ 0x00, 0x00, 0x1e, 0xc8, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x11,
+ 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x23,
+ 0x00, 0x00, 0x1e, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03,
+ 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x01,
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+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+};
+
+const size_t imxrt_dtb_size = sizeof(imxrt_dtb);
diff --git a/bsps/arm/imxrt/dts/imxrt1050-evkb.dts b/bsps/arm/imxrt/dts/imxrt1050-evkb.dts
new file mode 100644
index 0000000000..968ca1dbdc
--- /dev/null
+++ b/bsps/arm/imxrt/dts/imxrt1050-evkb.dts
@@ -0,0 +1,410 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * FIXME: Compilation should be automated.
+ *
+ * Compile this file with the following commands:
+ * export BSP_DIR="${RTEMS_SRC_DIR}/bsps/arm/imxrt/"
+ * arm-rtems6-cpp -P -x assembler-with-cpp -I "${BSP_DIR}/include/" -include "${BSP_DIR}/dts/imxrt1050-evkb.dts" /dev/null | \
+ * dtc -@ -O dtb -o "${BSP_DIR}/dts/imxrt1050-evkb.dtb" -b 0 -p 1024
+ * rtems-bin2c -C -N imxrt_dtb "${BSP_DIR}/dts/imxrt1050-evkb.dtb" "${BSP_DIR}/dts/imxrt1050-evkb.c"
+ */
+
+#include <imxrt/imxrt1050-pinfunc.h>
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ chosen: chosen {};
+
+ aliases {
+ gpio0 = &gpio1;
+ gpio1 = &gpio2;
+ gpio2 = &gpio3;
+ gpio3 = &gpio4;
+ gpio4 = &gpio5;
+ };
+
+ nvic: interrupt-controller at e000e100 {
+ compatible = "arm,armv7m-nvic";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0xe000e100 0xc00>;
+ };
+
+ systick: timer at e000e010 {
+ compatible = "arm,armv7m-systick";
+ reg = <0xe000e010 0x10>;
+ status = "disabled";
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&nvic>;
+ ranges;
+
+ aips-bus at 40000000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x40000000 0x00100000>;
+ ranges;
+
+ gpio5: gpio at 400c0000 {
+ compatible = "fsl,imxrt-gpio",
+ "fsl,imx6ul-gpio", "fsl,imx35-gpio";
+ reg = <0x400c0000 0x4000>;
+ interrupts = <88>, <89>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ aips-bus at 40100000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x40100000 0x00100000>;
+ ranges;
+
+ gpio4: gpio at 401c4000 {
+ compatible = "fsl,imxrt-gpio",
+ "fsl,imx6ul-gpio", "fsl,imx35-gpio";
+ reg = <0x401c4000 0x4000>;
+ interrupts = <86>, <87>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio at 401c0000 {
+ compatible = "fsl,imxrt-gpio",
+ "fsl,imx6ul-gpio", "fsl,imx35-gpio";
+ reg = <0x401c0000 0x4000>;
+ interrupts = <84>, <85>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio at 401bc000 {
+ compatible = "fsl,imxrt-gpio",
+ "fsl,imx6ul-gpio", "fsl,imx35-gpio";
+ reg = <0x401bc000 0x4000>;
+ interrupts = <82>, <83>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio at 401b8000 {
+ compatible = "fsl,imxrt-gpio",
+ "fsl,imx6ul-gpio", "fsl,imx35-gpio";
+ reg = <0x401b8000 0x4000>;
+ interrupts = <80>, <81>, <72>, <73>, <74>,
+ <75>, <76>, <77>, <78>, <79>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ lpuart1: uart at 40184000 {
+ compatible = "nxp,imxrt-lpuart";
+ reg = <0x40184000 0x4000>;
+ interrupts = <20>;
+ status = "disabled";
+ rtems,path = "/dev/ttyS1";
+ };
+
+ lpuart2: uart at 40188000 {
+ compatible = "nxp,imxrt-lpuart";
+ reg = <0x40188000 0x4000>;
+ interrupts = <21>;
+ status = "disabled";
+ rtems,path = "/dev/ttyS2";
+ };
+
+ lpuart3: uart at 4018c000 {
+ compatible = "nxp,imxrt-lpuart";
+ reg = <0x4018c000 0x4000>;
+ interrupts = <22>;
+ status = "disabled";
+ rtems,path = "/dev/ttyS3";
+ };
+
+ lpuart4: uart at 40190000 {
+ compatible = "nxp,imxrt-lpuart";
+ reg = <0x40190000 0x4000>;
+ interrupts = <23>;
+ status = "disabled";
+ rtems,path = "/dev/ttyS4";
+ };
+
+ lpuart5: uart at 40194000 {
+ compatible = "nxp,imxrt-lpuart";
+ reg = <0x40194000 0x4000>;
+ interrupts = <24>;
+ status = "disabled";
+ rtems,path = "/dev/ttyS5";
+ };
+
+ lpuart6: uart at 40198000 {
+ compatible = "nxp,imxrt-lpuart";
+ reg = <0x40198000 0x4000>;
+ interrupts = <25>;
+ status = "disabled";
+ rtems,path = "/dev/ttyS6";
+ };
+
+ lpuart7: uart at 4019c000 {
+ compatible = "nxp,imxrt-lpuart";
+ reg = <0x4019c000 0x4000>;
+ interrupts = <26>;
+ status = "disabled";
+ rtems,path = "/dev/ttyS7";
+ };
+
+ lpuart8: uart at 401a0000 {
+ compatible = "nxp,imxrt-lpuart";
+ reg = <0x401a0000 0x4000>;
+ interrupts = <27>;
+ status = "disabled";
+ rtems,path = "/dev/ttyS8";
+ };
+
+ iomuxc: pinctrl at 401f8000 {
+ compatible = "nxp,imxrt1050-iomuxc";
+ reg = <0x401f8000 0x4000>;
+ };
+ };
+
+ aips-bus at 40200000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x40200000 0x00100000>;
+ ranges;
+
+ fec1: ethernet at 402d8000 {
+ compatible = "fsl,imxrt-fec", "fsl,imx6ul-fec";
+ reg = <0x402d8000 0x4000>;
+ interrupt-names = "int0", "pps";
+ interrupts = <114>, <115>;
+ fsl,num-tx-queues = <1>;
+ fsl,num-rx-queues = <1>;
+ phy-mode = "rmii";
+ status = "disabled";
+ };
+ };
+
+ aips-bus at 40300000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x40300000 0x00100000>;
+ ranges;
+
+ lpspi1: lpspi at 40394000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nxp,imxrt-lpspi";
+ reg = <0x40394000 0x4000>;
+ interrupts = <32>;
+ status = "disabled";
+ rtems,path = "/dev/spi1";
+ };
+
+ lpspi2: lpspi at 40398000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nxp,imxrt-lpspi";
+ reg = <0x40398000 0x4000>;
+ interrupts = <33>;
+ status = "disabled";
+ rtems,path = "/dev/spi2";
+ };
+
+ lpspi3: lpspi at 4039c000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nxp,imxrt-lpspi";
+ reg = <0x4039c000 0x4000>;
+ interrupts = <34>;
+ status = "disabled";
+ rtems,path = "/dev/spi3";
+ };
+
+ lpspi4: lpspi at 403a0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nxp,imxrt-lpspi";
+ reg = <0x403a0000 0x4000>;
+ interrupts = <35>;
+ status = "disabled";
+ rtems,path = "/dev/spi4";
+ };
+
+ lpi2c1: lpi2c at 403f0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nxp,imxrt-lpi2c";
+ reg = <0x403f0000 0x4000>;
+ interrupts = <28>;
+ status = "disabled";
+ rtems,path = "/dev/i2c1";
+ };
+
+ lpi2c2: lpi2c at 403f4000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nxp,imxrt-lpi2c";
+ reg = <0x403f4000 0x4000>;
+ interrupts = <29>;
+ status = "disabled";
+ rtems,path = "/dev/i2c2";
+ };
+
+ lpi2c3: lpi2c at 403f8000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nxp,imxrt-lpi2c";
+ reg = <0x403f8000 0x4000>;
+ interrupts = <30>;
+ status = "disabled";
+ rtems,path = "/dev/i2c3";
+ };
+
+ lpi2c4: lpi2c at 403fc000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nxp,imxrt-lpi2c";
+ reg = <0x403fc000 0x4000>;
+ interrupts = <31>;
+ status = "disabled";
+ rtems,path = "/dev/i2c4";
+ };
+ };
+ };
+};
+
+&lpuart1 {
+ pinctrl-0 = <&pinctrl_lpuart1>;
+ status = "okay";
+};
+
+&chosen {
+ stdout-path = &lpuart1;
+};
+
+&lpuart3 {
+ pinctrl-0 = <&pinctrl_lpuart3>;
+ status = "okay";
+};
+
+&lpspi1 {
+ pinctrl-0 = <&pinctrl_lpspi1>;
+ status = "okay";
+};
+
+&lpi2c1 {
+ pinctrl-0 = <&pinctrl_lpi2c1>;
+ status = "okay";
+};
+
+&lpi2c1 {
+ pinctrl-0 = <&pinctrl_lpi2c1>;
+ status = "okay";
+};
+
+&fec1 {
+ pinctrl-0 = <&pinctrl_fec1>;
+ phy-reset-gpios = <&gpio1 9 1>;
+ rtems,phy-interrupt-gpios = <&gpio1 10 1>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_lpuart1: lpuart1grp {
+ fsl,pins = <
+ IMXRT_PAD_GPIO_AD_B0_12__LPUART1_TX 0x8
+ IMXRT_PAD_GPIO_AD_B0_13__LPUART1_RX 0x13000
+ >;
+ };
+
+ pinctrl_lpuart3: lpuart3grp {
+ fsl,pins = <
+ IMXRT_PAD_GPIO_AD_B1_06__LPUART3_TX 0x8
+ IMXRT_PAD_GPIO_AD_B1_07__LPUART3_RX 0x13000
+ >;
+ };
+
+ pinctrl_lpspi1: lpspi1grp {
+ fsl,pins = <
+ IMXRT_PAD_GPIO_SD_B0_01__LPSPI1_PCS0 0x8
+ IMXRT_PAD_GPIO_SD_B0_02__LPSPI1_SDO 0x8
+ IMXRT_PAD_GPIO_SD_B0_03__LPSPI1_SDI 0x1b000
+ IMXRT_PAD_GPIO_SD_B0_00__LPSPI1_SCK 0x8
+ >;
+ };
+
+ pinctrl_lpi2c1: lpi2c1grp {
+ fsl,pins = <
+ IMXRT_PAD_GPIO_AD_B1_00__LPI2C1_SCL 0x4000f830
+ IMXRT_PAD_GPIO_AD_B1_01__LPI2C1_SDA 0x4000f830
+ >;
+ };
+
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ IMXRT_PAD_GPIO_EMC_41__ENET_enet_mdio 0xb829
+ IMXRT_PAD_GPIO_EMC_40__ENET_enet_mdc 0xb0e9
+ IMXRT_PAD_GPIO_B1_04__ENET_enet_rx_data0 0xb0e9
+ IMXRT_PAD_GPIO_B1_05__ENET_enet_rx_data1 0xb0e9
+ IMXRT_PAD_GPIO_B1_06__ENET_enet_rx_en 0xb0e9
+ IMXRT_PAD_GPIO_B1_07__ENET_enet_tx_data0 0xb0e9
+ IMXRT_PAD_GPIO_B1_08__ENET_enet_tx_data1 0xb0e9
+ IMXRT_PAD_GPIO_B1_09__ENET_enet_tx_en 0xb0e9
+ IMXRT_PAD_GPIO_B1_10__ENET_enet_ref_clk 0x40000031
+ IMXRT_PAD_GPIO_B1_11__ENET_enet_rx_er 0xb0e9
+ /* ENET_RST */
+ IMXRT_PAD_GPIO_AD_B0_09__GPIO1_gpio_io09 0x810
+ /* ENET_INT */
+ IMXRT_PAD_GPIO_AD_B0_10__GPIO1_gpio_io10 0xb0a9
+ >;
+ };
+};
diff --git a/bsps/arm/imxrt/i2c/imxrt-lpi2c.c b/bsps/arm/imxrt/i2c/imxrt-lpi2c.c
new file mode 100644
index 0000000000..783c6e18e6
--- /dev/null
+++ b/bsps/arm/imxrt/i2c/imxrt-lpi2c.c
@@ -0,0 +1,489 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <bsp.h>
+#include <bsp/fatal.h>
+#include <bsp/fdt.h>
+#include <bsp/irq.h>
+
+#include <chip.h>
+#include <dev/i2c/i2c.h>
+#include <fsl_clock.h>
+#include <fsl_lpi2c.h>
+#include <libfdt.h>
+
+#define LPI2C_MTDR_CMD_transmit LPI2C_MTDR_CMD(0)
+#define LPI2C_MTDR_CMD_receive LPI2C_MTDR_CMD(1)
+#define LPI2C_MTDR_CMD_stop LPI2C_MTDR_CMD(2)
+#define LPI2C_MTDR_CMD_receive_and_discard LPI2C_MTDR_CMD(3)
+#define LPI2C_MTDR_CMD_start_and_transmit LPI2C_MTDR_CMD(4)
+#define LPI2C_MTDR_CMD_start_and_transmit_NACK LPI2C_MTDR_CMD(5)
+#define LPI2C_MTDR_CMD_start_and_transmit_highspeed LPI2C_MTDR_CMD(6)
+#define LPI2C_MTDR_CMD_start_and_transmit_highspeed_NACK LPI2C_MTDR_CMD(7)
+
+#define LPI2C_INT_ERRORS_SERIOUS ( \
+ LPI2C_MSR_FEF_MASK | LPI2C_MSR_ALF_MASK | LPI2C_MSR_PLTF_MASK )
+
+#define LPI2C_INT_ERROR_NO_ACK (LPI2C_MSR_NDF_MASK)
+
+#define LPI2C_INT_ERRORS (LPI2C_INT_ERRORS_SERIOUS | LPI2C_INT_ERROR_NO_ACK)
+
+#define LPI2C_INT_ADDRESSED (LPI2C_INT_ERRORS | LPI2C_MSR_TDF_MASK)
+
+#define LPI2C_INT_STOP_SENT (LPI2C_INT_ERRORS | LPI2C_MSR_SDF_MASK)
+
+#define LPI2C_INT_RECEIVED (LPI2C_INT_ERRORS | LPI2C_MSR_RDF_MASK)
+
+#define LPI2C_INT_TRANSMITTED (LPI2C_INT_ERRORS | LPI2C_MSR_TDF_MASK)
+
+struct imxrt_lpi2c_bus {
+ i2c_bus base;
+ volatile LPI2C_Type *regs;
+ rtems_vector_number irq;
+ uint32_t src_clock_hz;
+ clock_ip_name_t clock_ip;
+ unsigned long clock;
+
+ rtems_binary_semaphore sem;
+ int eno;
+
+ uint32_t msg_todo;
+ const i2c_msg *msg;
+
+ /* Everything that is necessary for the current message */
+ uint32_t chunk_todo;
+ uint16_t buf_todo;
+ uint8_t *buf;
+ bool stop;
+ bool read;
+};
+
+static void imxrt_lpi2c_sw_reset(volatile LPI2C_Type *regs)
+{
+ regs->MCR = LPI2C_MCR_RST_MASK | LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK;
+ regs->SCR = LPI2C_SCR_RST_MASK | LPI2C_SCR_RRF_MASK | LPI2C_SCR_RTF_MASK;
+ regs->MCR = 0;
+ regs->SCR = 0;
+}
+
+static int imxrt_lpi2c_set_clock(i2c_bus *base, unsigned long clock)
+{
+ struct imxrt_lpi2c_bus *bus;
+ volatile LPI2C_Type *regs;
+
+ bus = (struct imxrt_lpi2c_bus *) base;
+ regs = bus->regs;
+
+ bus->clock = clock;
+
+ /*
+ * Maybe there is a more efficient way than used by that function. But
+ * changing clock doesn't happen often. So it should be OK for now.
+ */
+ LPI2C_MasterSetBaudRate((LPI2C_Type *)regs, bus->src_clock_hz, clock);
+
+ return 0;
+}
+
+static void imxrt_lpi2c_do_reinit(
+ struct imxrt_lpi2c_bus *bus,
+ volatile LPI2C_Type *regs
+)
+{
+ regs->MIER = 0;
+ imxrt_lpi2c_sw_reset(regs);
+
+ regs->MCFGR2 = LPI2C_MCFGR2_FILTSDA(0) | LPI2C_MCFGR2_FILTSCL(0) |
+ LPI2C_MCFGR2_BUSIDLE(0);
+ regs->MCFGR3 = LPI2C_MCFGR3_PINLOW(0);
+
+ regs->MFCR = LPI2C_MFCR_RXWATER(0) | LPI2C_MFCR_TXWATER(1);
+
+ imxrt_lpi2c_set_clock(&bus->base, bus->clock);
+}
+
+static void imxrt_lpi2c_done(
+ struct imxrt_lpi2c_bus *bus,
+ volatile LPI2C_Type *regs
+)
+{
+ regs->MIER = 0;
+ regs->MCR &= ~LPI2C_MCR_MEN_MASK;
+ rtems_binary_semaphore_post(&bus->sem);
+}
+
+static void imxrt_lpi2c_next_msg(
+ struct imxrt_lpi2c_bus *bus,
+ volatile LPI2C_Type *regs
+);
+
+static void imxrt_lpi2c_transmit_next(
+ struct imxrt_lpi2c_bus *bus,
+ volatile LPI2C_Type *regs
+)
+{
+ if (bus->chunk_todo == 0) {
+ /* Check whether a stop has to be send */
+ if (bus->stop) {
+ regs->MTDR = LPI2C_MTDR_CMD_stop;
+ bus->stop = false;
+ regs->MIER = LPI2C_INT_STOP_SENT;
+ } else {
+ imxrt_lpi2c_next_msg(bus, regs);
+ }
+ } else {
+ if (bus->read) {
+ uint16_t to_read;
+ to_read = MIN(bus->chunk_todo, 256);
+ bus->chunk_todo -= to_read;
+
+ regs->MTDR = LPI2C_MTDR_CMD_receive | (to_read - 1);
+ regs->MIER = LPI2C_INT_RECEIVED;
+ } else {
+ regs->MTDR = LPI2C_MTDR_CMD_transmit | *bus->buf;
+ ++bus->buf;
+ --bus->buf_todo;
+ --bus->chunk_todo;
+ regs->MIER = LPI2C_INT_TRANSMITTED;
+ }
+ }
+}
+
+static void imxrt_lpi2c_next_msg(
+ struct imxrt_lpi2c_bus *bus,
+ volatile LPI2C_Type *regs
+)
+{
+ if (bus->msg_todo == 0) {
+ imxrt_lpi2c_done(bus, regs);
+ } else {
+ const i2c_msg *msg;
+ int flags;
+ bool start;
+ uint16_t addr;
+
+ msg = bus->msg;
+ flags = msg->flags;
+
+ addr = msg->addr;
+ start = (flags & I2C_M_NOSTART) == 0;
+ bus->read = (flags & I2C_M_RD) != 0;
+ bus->chunk_todo = msg->len;
+ bus->buf_todo = msg->len;
+ bus->buf = msg->buf;
+ bus->stop = (flags & I2C_M_STOP) != 0 || bus->msg_todo <= 1;
+
+ ++bus->msg;
+ --bus->msg_todo;
+
+ if (start) {
+ uint32_t mtdr;
+ mtdr = LPI2C_MTDR_CMD_start_and_transmit;
+ mtdr |= addr << 1;
+ if (bus->read) {
+ mtdr |= 1;
+ }
+ regs->MTDR = mtdr;
+ regs->MIER = LPI2C_INT_ADDRESSED;
+ } else {
+ imxrt_lpi2c_transmit_next(bus, regs);
+ }
+ }
+}
+
+static void imxrt_lpi2c_interrupt(void *arg)
+{
+ struct imxrt_lpi2c_bus *bus;
+ volatile LPI2C_Type *regs;
+ uint32_t msr;
+
+ bus = arg;
+ regs = bus->regs;
+
+ msr = regs->MSR;
+ regs->MSR = msr;
+
+ if ((msr & LPI2C_INT_ERROR_NO_ACK) != 0) {
+ /* Just end the transmission */
+ bus->eno = EIO;
+ imxrt_lpi2c_done(bus, regs);
+ } else if ((msr & LPI2C_INT_ERRORS_SERIOUS) != 0) {
+ /* Some worse error occurred. Reset hardware. */
+ bus->eno = EIO;
+ imxrt_lpi2c_do_reinit(bus, regs);
+ imxrt_lpi2c_done(bus, regs);
+ } else {
+ uint32_t mrdr;
+ while (((mrdr = regs->MRDR) & LPI2C_MRDR_RXEMPTY_MASK) == 0) {
+ if (bus->read && bus->buf_todo > 0) {
+ *bus->buf = (mrdr & LPI2C_MRDR_DATA_MASK) >> LPI2C_MRDR_DATA_SHIFT;
+ ++bus->buf;
+ --bus->buf_todo;
+ }
+ }
+
+ if (
+ ((msr & LPI2C_MSR_TDF_MASK) != 0) &&
+ (!bus->read || bus->chunk_todo > 0 || bus->buf_todo == 0)
+ ) {
+ imxrt_lpi2c_transmit_next(bus, regs);
+ }
+ }
+}
+
+static int imxrt_lpi2c_wait_for_not_busy(volatile LPI2C_Type *regs)
+{
+ rtems_interval timeout;
+ bool before;
+
+ if ((regs->MSR & LPI2C_MSR_BBF_MASK) == 0) {
+ return 0;
+ }
+
+ timeout = rtems_clock_tick_later_usec(5000);
+
+ do {
+ before = rtems_clock_tick_before(timeout);
+
+ if ((regs->MSR & LPI2C_MSR_BBF_MASK) == 0) {
+ return 0;
+ }
+ } while (before);
+
+ return ETIMEDOUT;
+}
+
+static void imxrt_lpi2c_first_msg(
+ struct imxrt_lpi2c_bus *bus,
+ volatile LPI2C_Type *regs
+)
+{
+ if ((regs->MCR & LPI2C_MCR_MEN_MASK) == 0) {
+ regs->MCR |= LPI2C_MCR_MEN_MASK;
+ }
+
+ imxrt_lpi2c_next_msg(bus, regs);
+}
+
+static int imxrt_lpi2c_transfer(i2c_bus *base, i2c_msg *msgs, uint32_t n)
+{
+ struct imxrt_lpi2c_bus *bus;
+ volatile LPI2C_Type *regs;
+ int supported_flags;
+ int eno;
+ uint16_t i;
+
+ bus = (struct imxrt_lpi2c_bus *) base;
+ regs = bus->regs;
+
+ supported_flags = I2C_M_RD | I2C_M_STOP;
+
+ for (i = 0; i < n; ++i) {
+ if ((msgs[i].flags & ~supported_flags) != 0) {
+ return -EINVAL;
+ }
+
+ supported_flags |= I2C_M_NOSTART;
+ }
+
+ eno = imxrt_lpi2c_wait_for_not_busy(regs);
+ if (eno != 0) {
+ imxrt_lpi2c_do_reinit(bus, regs);
+ return -eno;
+ }
+
+ bus->msg_todo = n;
+ bus->msg = &msgs[0];
+ bus->eno = 0;
+
+ imxrt_lpi2c_first_msg(bus, regs);
+
+ eno = rtems_binary_semaphore_wait_timed_ticks(&bus->sem, bus->base.timeout);
+ if (eno != 0) {
+ /* Timeout */
+ imxrt_lpi2c_do_reinit(bus, regs);
+ rtems_binary_semaphore_try_wait(&bus->sem);
+ return -eno;
+ }
+
+ return -bus->eno;
+}
+
+static void imxrt_lpi2c_destroy(i2c_bus *base)
+{
+ struct imxrt_lpi2c_bus *bus;
+ volatile LPI2C_Type *regs;
+
+ bus = (struct imxrt_lpi2c_bus *) base;
+ regs = bus->regs;
+ imxrt_lpi2c_sw_reset(regs);
+ CLOCK_DisableClock(bus->clock_ip);
+
+ rtems_interrupt_handler_remove(bus->irq, imxrt_lpi2c_interrupt, bus);
+ i2c_bus_destroy_and_free(&bus->base);
+}
+
+static int imxrt_lpi2c_hw_init(struct imxrt_lpi2c_bus *bus)
+{
+ rtems_status_code sc;
+ volatile LPI2C_Type *regs;
+
+ regs = bus->regs;
+
+ CLOCK_EnableClock(bus->clock_ip);
+
+ bus->clock = I2C_BUS_CLOCK_DEFAULT;
+ imxrt_lpi2c_do_reinit(bus, regs);
+
+ sc = rtems_interrupt_handler_install(
+ bus->irq,
+ "LPI2C",
+ RTEMS_INTERRUPT_UNIQUE,
+ imxrt_lpi2c_interrupt,
+ bus
+ );
+ if (sc != RTEMS_SUCCESSFUL) {
+ return EAGAIN;
+ }
+
+ return 0;
+}
+
+static uint32_t imxrt_lpi2c_get_src_freq(void)
+{
+ uint32_t freq;
+ uint32_t mux;
+ uint32_t divider;
+
+ mux = CLOCK_GetMux(kCLOCK_Lpi2cMux);
+ divider = 1;
+
+ switch (mux) {
+ case 0: /* pll3_sw_clk */
+ freq = CLOCK_GetFreq(kCLOCK_Usb1PllClk);
+ divider = 8;
+ break;
+ case 1: /* OSC */
+ freq = CLOCK_GetFreq(kCLOCK_OscClk);
+ break;
+ default:
+ freq = 0;
+ }
+
+ divider *= CLOCK_GetDiv(kCLOCK_Lpi2cDiv) + 1;
+ freq /= divider;
+
+ return freq;
+}
+
+static clock_ip_name_t imxrt_lpi2c_clock_ip(volatile LPI2C_Type *regs)
+{
+ LPI2C_Type *const base_addresses[] = LPI2C_BASE_PTRS;
+ static const clock_ip_name_t lpi2c_clocks[] = LPI2C_CLOCKS;
+ size_t i;
+
+ for (i = 0; i < RTEMS_ARRAY_SIZE(base_addresses); ++i) {
+ if (base_addresses[i] == regs) {
+ return lpi2c_clocks[i];
+ }
+ }
+
+ return kCLOCK_IpInvalid;
+}
+
+void imxrt_lpi2c_init(void)
+{
+ const void *fdt;
+ int node;
+
+ fdt = bsp_fdt_get();
+ node = -1;
+
+ do {
+ node = fdt_node_offset_by_compatible(fdt, node, "nxp,imxrt-lpi2c");
+
+ if (node >= 0 && imxrt_fdt_node_is_enabled(fdt, node)) {
+ struct imxrt_lpi2c_bus *bus;
+ int eno;
+ const char *bus_path;
+
+ bus = (struct imxrt_lpi2c_bus*) i2c_bus_alloc_and_init(sizeof(*bus));
+ if (bus == NULL) {
+ bsp_fatal(IMXRT_FATAL_LPI2C_ALLOC_FAILED);
+ }
+
+ rtems_binary_semaphore_init(&bus->sem, "LPI2C");
+
+ bus->regs = imx_get_reg_of_node(fdt, node);
+ if (bus->regs == NULL) {
+ (*bus->base.destroy)(&bus->base);
+ bsp_fatal(IMXRT_FATAL_LPI2C_INVALID_FDT);
+ }
+
+ bus->irq = imx_get_irq_of_node(fdt, node, 0);
+ if (bus->irq == BSP_INTERRUPT_VECTOR_INVALID) {
+ (*bus->base.destroy)(&bus->base);
+ bsp_fatal(IMXRT_FATAL_LPI2C_INVALID_FDT);
+ }
+
+ bus_path = fdt_getprop(fdt, node, "rtems,path", NULL);
+ if (bus_path == NULL) {
+ (*bus->base.destroy)(&bus->base);
+ bsp_fatal(IMXRT_FATAL_LPI2C_INVALID_FDT);
+ }
+
+ bus->clock_ip = imxrt_lpi2c_clock_ip(bus->regs);
+ bus->src_clock_hz = imxrt_lpi2c_get_src_freq();
+
+ eno = imxrt_lpi2c_hw_init(bus);
+ if (eno != 0) {
+ (*bus->base.destroy)(&bus->base);
+ bsp_fatal(IMXRT_FATAL_LPI2C_HW_INIT_FAILED);
+ }
+
+ bus->base.transfer = imxrt_lpi2c_transfer;
+ bus->base.set_clock = imxrt_lpi2c_set_clock;
+ bus->base.destroy = imxrt_lpi2c_destroy;
+
+ /*
+ * Need at least three FIFO bytes:
+ * 1. One to two data to transmit or receive.
+ * Two is necessary for long receives without NACK.
+ * 2. A stop condition.
+ */
+ if ((1 << ((bus->regs->PARAM & LPI2C_PARAM_MTXFIFO_MASK) >>
+ LPI2C_PARAM_MTXFIFO_SHIFT)) < 3) {
+ bsp_fatal(IMXRT_FATAL_LPI2C_UNSUPPORTED_HARDWARE);
+ }
+
+ eno = i2c_bus_register(&bus->base, bus_path);
+ if (eno != 0) {
+ bsp_fatal(IMXRT_FATAL_LPI2C_REGISTER_FAILED);
+ }
+ }
+ } while (node >= 0);
+}
diff --git a/bsps/arm/imxrt/include/bsp.h b/bsps/arm/imxrt/include/bsp.h
new file mode 100644
index 0000000000..f93c28aee0
--- /dev/null
+++ b/bsps/arm/imxrt/include/bsp.h
@@ -0,0 +1,93 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsARMimxrt
+ */
+
+/*
+ * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_ARM_IMXRT_BSP_H
+#define LIBBSP_ARM_IMXRT_BSP_H
+
+/**
+ * @defgroup RTEMSBSPsARMimxrt NXP i.MXRT
+ *
+ * @ingroup RTEMSBSPsARM
+ *
+ * @brief NXP i.MXRT Board Support Package.
+ *
+ * @{
+ */
+
+#include <bspopts.h>
+
+#include <rtems.h>
+
+#include <bsp/default-initial-extension.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#define BSP_FEATURE_IRQ_EXTENSION
+
+#define BSP_FDT_IS_SUPPORTED
+extern const unsigned char imxrt_dtb[];
+extern const size_t imxrt_dtb_size;
+
+void *imx_get_reg_of_node(const void *fdt, int node);
+
+rtems_vector_number imx_get_irq_of_node(
+ const void *fdt,
+ int node,
+ size_t index
+);
+
+bool imxrt_fdt_node_is_enabled(const void *fdt, int node);
+
+/*
+ * About 50% between `basepri` in arm_interrupt_disable and the maximum for this
+ * chip.
+ */
+#define BSP_ARMV7M_IRQ_PRIORITY_DEFAULT (13 << 4)
+#define BSP_ARMV7M_SYSTICK_PRIORITY (14 << 4)
+
+#define BSP_ARMV7M_SYSTICK_FREQUENCY imxrt_systick_frequency()
+uint32_t imxrt_systick_frequency(void);
+
+void imxrt_lpspi_init(void);
+void imxrt_lpi2c_init(void);
+void imxrt_ffec_init(void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+/* @} */
+
+#endif /* LIBBSP_ARM_IMXRT_BSP_H */
diff --git a/bsps/arm/imxrt/include/bsp/flash-headers.h b/bsps/arm/imxrt/include/bsp/flash-headers.h
new file mode 100644
index 0000000000..6575b1c21b
--- /dev/null
+++ b/bsps/arm/imxrt/include/bsp/flash-headers.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsARMimxrt
+ *
+ * @brief Header structures that are used by i.MXRT1050 for booting from flash.
+ */
+
+/*
+ * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_ARM_IMXRT_FLASH_HEADERS_H
+#define LIBBSP_ARM_IMXRT_FLASH_HEADERS_H
+
+#include <stdint.h>
+#include <fsl_flexspi_nor_config.h>
+#include <fsl_flexspi_nor_boot.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+__attribute__((section(".boot_hdr.dcd_data")))
+extern const uint8_t imxrt_dcd_data[];
+
+__attribute__((section(".boot_hdr.ivt")))
+extern const ivt imxrt_image_vector_table;
+
+__attribute__((section(".boot_hdr.boot_data")))
+extern const BOOT_DATA_T imxrt_boot_data;
+
+__attribute__((section(".boot_hdr.conf")))
+extern const flexspi_nor_config_t imxrt_flexspi_config;
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_IMXRT_FLASH_HEADERS_H */
diff --git a/bsps/arm/imxrt/include/bsp/irq.h b/bsps/arm/imxrt/include/bsp/irq.h
new file mode 100644
index 0000000000..eed54f8648
--- /dev/null
+++ b/bsps/arm/imxrt/include/bsp/irq.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsARMimxrt
+ */
+
+/*
+ * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_ARM_IMXRT_IRQ_H
+#define LIBBSP_ARM_IMXRT_IRQ_H
+
+#ifndef ASM
+ #include <rtems/irq.h>
+ #include <rtems/irq-extension.h>
+#endif /* ASM */
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#define BSP_INTERRUPT_VECTOR_MIN 0
+#define BSP_INTERRUPT_VECTOR_MAX 159
+#define BSP_INTERRUPT_VECTOR_INVALID (UINT32_MAX)
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_IMXRT_IRQ_H */
diff --git a/bsps/arm/imxrt/include/chip.h b/bsps/arm/imxrt/include/chip.h
new file mode 100644
index 0000000000..9ea618edd1
--- /dev/null
+++ b/bsps/arm/imxrt/include/chip.h
@@ -0,0 +1,2 @@
+#include "MIMXRT1052.h"
+#include "MIMXRT1052_features.h"
diff --git a/bsps/arm/imxrt/include/imxrt/imxrt1050-pinfunc.h b/bsps/arm/imxrt/include/imxrt/imxrt1050-pinfunc.h
new file mode 100644
index 0000000000..16ebfae5b3
--- /dev/null
+++ b/bsps/arm/imxrt/include/imxrt/imxrt1050-pinfunc.h
@@ -0,0 +1,1236 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsARMimxrt
+ *
+ * @brief Pin function definitions for i.MXRT1050
+ */
+
+/*
+ * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_ARM_IMXRT_IMXRT1050_PINFUNC_H
+#define LIBBSP_ARM_IMXRT_IMXRT1050_PINFUNC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* GPIO_AD_B0_00 */
+#define IMXRT_PAD_GPIO_AD_B0_00__PWM2_A3 0x00bc 0x02ac 0x0474 0 2
+#define IMXRT_PAD_GPIO_AD_B0_00__XBARA1_OUT14 0x00bc 0x02ac 0x0644 1 0 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_14 to 0x1 */
+#define IMXRT_PAD_GPIO_AD_B0_00__XBARA1_IN14 0x00bc 0x02ac 0x0644 1 0 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_14 to 0 */
+#define IMXRT_PAD_GPIO_AD_B0_00__XTALOSC24M_REF_CLK_32K 0x00bc 0x02ac 0x0000 2 0
+#define IMXRT_PAD_GPIO_AD_B0_00__USB2_usb_otg2_id 0x00bc 0x02ac 0x03f8 3 0
+#define IMXRT_PAD_GPIO_AD_B0_00__LPI2C1_SCLS 0x00bc 0x02ac 0x0000 4 0
+#define IMXRT_PAD_GPIO_AD_B0_00__GPIO1_gpio_io00 0x00bc 0x02ac 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B0_00__USDHC1_usdhc_reset_b 0x00bc 0x02ac 0x0000 6 0
+#define IMXRT_PAD_GPIO_AD_B0_00__LPSPI3_SCK 0x00bc 0x02ac 0x0510 7 0
+#define IMXRT_PAD_GPIO_AD_B0_00__CMP1_IN4 0x00bc 0x02ac 0x0000 5 0
+
+/* GPIO_AD_B0_01 */
+#define IMXRT_PAD_GPIO_AD_B0_01__PWM2_B3 0x00c0 0x02b0 0x0484 0 2
+#define IMXRT_PAD_GPIO_AD_B0_01__XBARA1_OUT15 0x00c0 0x02b0 0x0648 1 0 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_15 to 0x1 */
+#define IMXRT_PAD_GPIO_AD_B0_01__XBARA1_IN15 0x00c0 0x02b0 0x0648 1 0 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_15 to 0 */
+#define IMXRT_PAD_GPIO_AD_B0_01__XTALOSC24M_REF_CLK_24M 0x00c0 0x02b0 0x0000 2 0
+#define IMXRT_PAD_GPIO_AD_B0_01__USB1_usb_otg1_id 0x00c0 0x02b0 0x03f4 3 0
+#define IMXRT_PAD_GPIO_AD_B0_01__LPI2C1_SDAS 0x00c0 0x02b0 0x0000 4 0
+#define IMXRT_PAD_GPIO_AD_B0_01__GPIO1_gpio_io01 0x00c0 0x02b0 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B0_01__EWM_EWM_OUT_B 0x00c0 0x02b0 0x0000 6 0
+#define IMXRT_PAD_GPIO_AD_B0_01__LPSPI3_SDO 0x00c0 0x02b0 0x0518 7 0
+#define IMXRT_PAD_GPIO_AD_B0_01__CMP2_IN4 0x00c0 0x02b0 0x0000 5 0
+
+/* GPIO_AD_B0_02 */
+#define IMXRT_PAD_GPIO_AD_B0_02__CAN2_TX 0x00c4 0x02b4 0x0000 0 0
+#define IMXRT_PAD_GPIO_AD_B0_02__XBARA1_OUT16 0x00c4 0x02b4 0x064c 1 0 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_16 to 0x1 */
+#define IMXRT_PAD_GPIO_AD_B0_02__XBARA1_IN16 0x00c4 0x02b4 0x064c 1 0 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_16 to 0 */
+#define IMXRT_PAD_GPIO_AD_B0_02__LPUART6_TX 0x00c4 0x02b4 0x0554 2 1
+#define IMXRT_PAD_GPIO_AD_B0_02__USB1_usb_otg1_pwr 0x00c4 0x02b4 0x0000 3 0
+#define IMXRT_PAD_GPIO_AD_B0_02__PWM1_X0 0x00c4 0x02b4 0x0000 4 0
+#define IMXRT_PAD_GPIO_AD_B0_02__GPIO1_gpio_io02 0x00c4 0x02b4 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B0_02__LPI2C1_HREQ 0x00c4 0x02b4 0x0000 6 0
+#define IMXRT_PAD_GPIO_AD_B0_02__LPSPI3_SDI 0x00c4 0x02b4 0x0514 7 0
+#define IMXRT_PAD_GPIO_AD_B0_02__CMP3_IN4 0x00c4 0x02b4 0x0000 5 0
+
+/* GPIO_AD_B0_03 */
+#define IMXRT_PAD_GPIO_AD_B0_03__CAN2_RX 0x00c8 0x02b8 0x0450 0 1
+#define IMXRT_PAD_GPIO_AD_B0_03__XBARA1_OUT17 0x00c8 0x02b8 0x062c 1 1 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_17 to 0x1 */
+#define IMXRT_PAD_GPIO_AD_B0_03__XBARA1_IN17 0x00c8 0x02b8 0x062c 1 1 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_17 to 0 */
+#define IMXRT_PAD_GPIO_AD_B0_03__LPUART6_RX 0x00c8 0x02b8 0x0550 2 1
+#define IMXRT_PAD_GPIO_AD_B0_03__USB1_usb_otg1_oc 0x00c8 0x02b8 0x05d0 3 0
+#define IMXRT_PAD_GPIO_AD_B0_03__PWM1_X1 0x00c8 0x02b8 0x0000 4 0
+#define IMXRT_PAD_GPIO_AD_B0_03__GPIO1_gpio_io03 0x00c8 0x02b8 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B0_03__XTALOSC24M_REF_CLK_24M 0x00c8 0x02b8 0x0000 6 0
+#define IMXRT_PAD_GPIO_AD_B0_03__LPSPI3_PCS0 0x00c8 0x02b8 0x050c 7 0
+#define IMXRT_PAD_GPIO_AD_B0_03__CMP4_IN4 0x00c8 0x02b8 0x0000 5 0
+
+/* GPIO_AD_B0_04 */
+#define IMXRT_PAD_GPIO_AD_B0_04__SRC_BOOT_MODE0 0x00cc 0x02bc 0x0000 0 0
+#define IMXRT_PAD_GPIO_AD_B0_04__MQS_RIGHT 0x00cc 0x02bc 0x0000 1 0
+#define IMXRT_PAD_GPIO_AD_B0_04__ENET_enet_tx_data3 0x00cc 0x02bc 0x0000 2 0
+#define IMXRT_PAD_GPIO_AD_B0_04__SAI2_sai_tx_sync 0x00cc 0x02bc 0x05c4 3 1
+#define IMXRT_PAD_GPIO_AD_B0_04__CSI_csi_data09 0x00cc 0x02bc 0x041c 4 1
+#define IMXRT_PAD_GPIO_AD_B0_04__GPIO1_gpio_io04 0x00cc 0x02bc 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B0_04__PIT_TRIGGER0 0x00cc 0x02bc 0x0000 6 0
+#define IMXRT_PAD_GPIO_AD_B0_04__LPSPI3_PCS1 0x00cc 0x02bc 0x0000 7 0
+
+/* GPIO_AD_B0_05 */
+#define IMXRT_PAD_GPIO_AD_B0_05__SRC_BOOT_MODE1 0x00d0 0x02c0 0x0000 0 0
+#define IMXRT_PAD_GPIO_AD_B0_05__MQS_LEFT 0x00d0 0x02c0 0x0000 1 0
+#define IMXRT_PAD_GPIO_AD_B0_05__ENET_enet_tx_data2 0x00d0 0x02c0 0x0000 2 0
+#define IMXRT_PAD_GPIO_AD_B0_05__SAI2_sai_tx_bclk 0x00d0 0x02c0 0x05c0 3 1
+#define IMXRT_PAD_GPIO_AD_B0_05__CSI_csi_data08 0x00d0 0x02c0 0x0418 4 1
+#define IMXRT_PAD_GPIO_AD_B0_05__GPIO1_gpio_io05 0x00d0 0x02c0 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B0_05__XBARA1_OUT17 0x00d0 0x02c0 0x062c 6 2 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_17 to 0x1 */
+#define IMXRT_PAD_GPIO_AD_B0_05__XBARA1_IN17 0x00d0 0x02c0 0x062c 6 2 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_17 to 0 */
+#define IMXRT_PAD_GPIO_AD_B0_05__LPSPI3_PCS2 0x00d0 0x02c0 0x0000 7 0
+
+/* GPIO_AD_B0_06 */
+#define IMXRT_PAD_GPIO_AD_B0_06__JTAG_TMS 0x00d4 0x02c4 0x0000 0 0
+#define IMXRT_PAD_GPIO_AD_B0_06__GPT2_gpt_compare1 0x00d4 0x02c4 0x0000 1 0
+#define IMXRT_PAD_GPIO_AD_B0_06__ENET_enet_rx_clk 0x00d4 0x02c4 0x0000 2 0
+#define IMXRT_PAD_GPIO_AD_B0_06__SAI2_sai_rx_bclk 0x00d4 0x02c4 0x05b4 3 1
+#define IMXRT_PAD_GPIO_AD_B0_06__CSI_csi_data07 0x00d4 0x02c4 0x0414 4 1
+#define IMXRT_PAD_GPIO_AD_B0_06__GPIO1_gpio_io06 0x00d4 0x02c4 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B0_06__XBARA1_OUT18 0x00d4 0x02c4 0x0630 6 1 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_18 to 0x1 */
+#define IMXRT_PAD_GPIO_AD_B0_06__XBARA1_IN18 0x00d4 0x02c4 0x0630 6 1 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_18 to 0 */
+#define IMXRT_PAD_GPIO_AD_B0_06__LPSPI3_PCS3 0x00d4 0x02c4 0x0000 7 0
+
+/* GPIO_AD_B0_07 */
+#define IMXRT_PAD_GPIO_AD_B0_07__JTAG_TCK 0x00d8 0x02c8 0x0000 0 0
+#define IMXRT_PAD_GPIO_AD_B0_07__GPT2_gpt_compare2 0x00d8 0x02c8 0x0000 1 0
+#define IMXRT_PAD_GPIO_AD_B0_07__ENET_enet_tx_er 0x00d8 0x02c8 0x0000 2 0
+#define IMXRT_PAD_GPIO_AD_B0_07__SAI2_sai_rx_sync 0x00d8 0x02c8 0x05bc 3 1
+#define IMXRT_PAD_GPIO_AD_B0_07__CSI_csi_data06 0x00d8 0x02c8 0x0410 4 1
+#define IMXRT_PAD_GPIO_AD_B0_07__GPIO1_gpio_io07 0x00d8 0x02c8 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B0_07__XBARA1_OUT19 0x00d8 0x02c8 0x0654 6 1 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_19 to 0x1 */
+#define IMXRT_PAD_GPIO_AD_B0_07__XBARA1_IN19 0x00d8 0x02c8 0x0654 6 1 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_19 to 0 */
+#define IMXRT_PAD_GPIO_AD_B0_07__ENET_1588_EVENT3_OUT 0x00d8 0x02c8 0x0000 7 0
+
+/* GPIO_AD_B0_08 */
+#define IMXRT_PAD_GPIO_AD_B0_08__JTAG_MOD 0x00dc 0x02cc 0x0000 0 0
+#define IMXRT_PAD_GPIO_AD_B0_08__GPT2_gpt_compare3 0x00dc 0x02cc 0x0000 1 0
+#define IMXRT_PAD_GPIO_AD_B0_08__ENET_enet_rx_data3 0x00dc 0x02cc 0x0000 2 0
+#define IMXRT_PAD_GPIO_AD_B0_08__SAI2_sai_rx_data 0x00dc 0x02cc 0x05b8 3 1
+#define IMXRT_PAD_GPIO_AD_B0_08__CSI_csi_data05 0x00dc 0x02cc 0x040c 4 1
+#define IMXRT_PAD_GPIO_AD_B0_08__GPIO1_gpio_io08 0x00dc 0x02cc 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B0_08__XBARA1_IN20 0x00dc 0x02cc 0x0634 6 1
+#define IMXRT_PAD_GPIO_AD_B0_08__ENET_1588_EVENT3_IN 0x00dc 0x02cc 0x0000 7 0
+
+/* GPIO_AD_B0_09 */
+#define IMXRT_PAD_GPIO_AD_B0_09__JTAG_TDI 0x00e0 0x02d0 0x0000 0 0
+#define IMXRT_PAD_GPIO_AD_B0_09__PWM2_A3 0x00e0 0x02d0 0x0474 1 3
+#define IMXRT_PAD_GPIO_AD_B0_09__ENET_enet_rx_data2 0x00e0 0x02d0 0x0000 2 0
+#define IMXRT_PAD_GPIO_AD_B0_09__SAI2_sai_tx_data 0x00e0 0x02d0 0x0000 3 0
+#define IMXRT_PAD_GPIO_AD_B0_09__CSI_csi_data04 0x00e0 0x02d0 0x0408 4 1
+#define IMXRT_PAD_GPIO_AD_B0_09__GPIO1_gpio_io09 0x00e0 0x02d0 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B0_09__XBARA1_IN21 0x00e0 0x02d0 0x0658 6 1
+#define IMXRT_PAD_GPIO_AD_B0_09__GPT2_gpt_clk 0x00e0 0x02d0 0x0000 7 0
+
+/* GPIO_AD_B0_10 */
+#define IMXRT_PAD_GPIO_AD_B0_10__JTAG_TDO 0x00e4 0x02d4 0x0000 0 0
+#define IMXRT_PAD_GPIO_AD_B0_10__PWM1_A3 0x00e4 0x02d4 0x0454 1 3
+#define IMXRT_PAD_GPIO_AD_B0_10__ENET_enet_crs 0x00e4 0x02d4 0x0000 2 0
+#define IMXRT_PAD_GPIO_AD_B0_10__SAI2_sai_mclk 0x00e4 0x02d4 0x05b0 3 1
+#define IMXRT_PAD_GPIO_AD_B0_10__CSI_csi_data03 0x00e4 0x02d4 0x0404 4 1
+#define IMXRT_PAD_GPIO_AD_B0_10__GPIO1_gpio_io10 0x00e4 0x02d4 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B0_10__XBARA1_IN22 0x00e4 0x02d4 0x0638 6 1
+#define IMXRT_PAD_GPIO_AD_B0_10__ENET_1588_EVENT0_OUT 0x00e4 0x02d4 0x0000 7 0
+
+/* GPIO_AD_B0_11 */
+#define IMXRT_PAD_GPIO_AD_B0_11__JTAG_TRSTB 0x00e8 0x02d8 0x0000 0 0
+#define IMXRT_PAD_GPIO_AD_B0_11__PWM1_B3 0x00e8 0x02d8 0x0464 1 3
+#define IMXRT_PAD_GPIO_AD_B0_11__ENET_enet_col 0x00e8 0x02d8 0x0000 2 0
+#define IMXRT_PAD_GPIO_AD_B0_11__WDOG1_wdog_b 0x00e8 0x02d8 0x0000 3 0
+#define IMXRT_PAD_GPIO_AD_B0_11__CSI_csi_data02 0x00e8 0x02d8 0x0400 4 1
+#define IMXRT_PAD_GPIO_AD_B0_11__GPIO1_gpio_io11 0x00e8 0x02d8 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B0_11__XBARA1_IN23 0x00e8 0x02d8 0x063c 6 1
+#define IMXRT_PAD_GPIO_AD_B0_11__ENET_1588_EVENT0_IN 0x00e8 0x02d8 0x0444 7 1
+
+/* GPIO_AD_B0_12 */
+#define IMXRT_PAD_GPIO_AD_B0_12__LPI2C4_SCL 0x00ec 0x02dc 0x04e4 0 1
+#define IMXRT_PAD_GPIO_AD_B0_12__CCM_PMIC_RDY 0x00ec 0x02dc 0x03fc 1 1
+#define IMXRT_PAD_GPIO_AD_B0_12__LPUART1_TX 0x00ec 0x02dc 0x0000 2 0
+#define IMXRT_PAD_GPIO_AD_B0_12__WDOG2_wdog_b 0x00ec 0x02dc 0x0000 3 0
+#define IMXRT_PAD_GPIO_AD_B0_12__PWM1_X2 0x00ec 0x02dc 0x0000 4 0
+#define IMXRT_PAD_GPIO_AD_B0_12__GPIO1_gpio_io12 0x00ec 0x02dc 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B0_12__ENET_1588_EVENT1_OUT 0x00ec 0x02dc 0x0000 6 0
+#define IMXRT_PAD_GPIO_AD_B0_12__ARM_arm_nmi 0x00ec 0x02dc 0x0568 7 0
+#define IMXRT_PAD_GPIO_AD_B0_12__ADC1_IN1 0x00ec 0x02dc 0x0000 5 0
+
+/* GPIO_AD_B0_13 */
+#define IMXRT_PAD_GPIO_AD_B0_13__LPI2C4_SDA 0x00f0 0x02e0 0x04e8 0 1
+#define IMXRT_PAD_GPIO_AD_B0_13__GPT1_gpt_clk 0x00f0 0x02e0 0x0000 1 0
+#define IMXRT_PAD_GPIO_AD_B0_13__LPUART1_RX 0x00f0 0x02e0 0x0000 2 0
+#define IMXRT_PAD_GPIO_AD_B0_13__EWM_EWM_OUT_B 0x00f0 0x02e0 0x0000 3 0
+#define IMXRT_PAD_GPIO_AD_B0_13__PWM1_X3 0x00f0 0x02e0 0x0000 4 0
+#define IMXRT_PAD_GPIO_AD_B0_13__GPIO1_gpio_io13 0x00f0 0x02e0 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B0_13__ENET_1588_EVENT1_IN 0x00f0 0x02e0 0x0000 6 0
+#define IMXRT_PAD_GPIO_AD_B0_13__XTALOSC24M_REF_CLK_24M 0x00f0 0x02e0 0x0000 7 0
+#define IMXRT_PAD_GPIO_AD_B0_13__ADC1_IN2 0x00f0 0x02e0 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B0_13__CMP1_IN2 0x00f0 0x02e0 0x0000 5 0
+
+/* GPIO_AD_B0_14 */
+#define IMXRT_PAD_GPIO_AD_B0_14__USB2_usb_otg2_oc 0x00f4 0x02e4 0x05cc 0 0
+#define IMXRT_PAD_GPIO_AD_B0_14__XBARA1_IN24 0x00f4 0x02e4 0x0640 1 1
+#define IMXRT_PAD_GPIO_AD_B0_14__LPUART1_CTS_B 0x00f4 0x02e4 0x0000 2 0
+#define IMXRT_PAD_GPIO_AD_B0_14__ENET_1588_EVENT0_OUT 0x00f4 0x02e4 0x0000 3 0
+#define IMXRT_PAD_GPIO_AD_B0_14__CSI_csi_vsync 0x00f4 0x02e4 0x0428 4 0
+#define IMXRT_PAD_GPIO_AD_B0_14__GPIO1_gpio_io14 0x00f4 0x02e4 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B0_14__CAN2_TX 0x00f4 0x02e4 0x0000 6 0
+#define IMXRT_PAD_GPIO_AD_B0_14__ADC1_IN3 0x00f4 0x02e4 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B0_14__CMP2_IN2 0x00f4 0x02e4 0x0000 5 0
+
+/* GPIO_AD_B0_15 */
+#define IMXRT_PAD_GPIO_AD_B0_15__USB2_usb_otg2_pwr 0x00f8 0x02e8 0x0000 0 0
+#define IMXRT_PAD_GPIO_AD_B0_15__XBARA1_IN25 0x00f8 0x02e8 0x0650 1 0
+#define IMXRT_PAD_GPIO_AD_B0_15__LPUART1_RTS_B 0x00f8 0x02e8 0x0000 2 0
+#define IMXRT_PAD_GPIO_AD_B0_15__ENET_1588_EVENT0_IN 0x00f8 0x02e8 0x0444 3 0
+#define IMXRT_PAD_GPIO_AD_B0_15__CSI_csi_hsync 0x00f8 0x02e8 0x0420 4 0
+#define IMXRT_PAD_GPIO_AD_B0_15__GPIO1_gpio_io15 0x00f8 0x02e8 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B0_15__CAN2_RX 0x00f8 0x02e8 0x0450 6 2
+#define IMXRT_PAD_GPIO_AD_B0_15__WDOG1_wdog_rst_b_deb 0x00f8 0x02e8 0x0000 7 0
+#define IMXRT_PAD_GPIO_AD_B0_15__ADC1_IN4 0x00f8 0x02e8 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B0_15__CMP3_IN2 0x00f8 0x02e8 0x0000 5 0
+
+/* GPIO_AD_B1_00 */
+#define IMXRT_PAD_GPIO_AD_B1_00__USB2_usb_otg2_id 0x00fc 0x02ec 0x03f8 0 1
+#define IMXRT_PAD_GPIO_AD_B1_00__TMR3_TIMER0 0x00fc 0x02ec 0x057c 1 1 /* Maybe you want to set IOMUXC_GPR_GPR6 QTIMER3_TRM0_INPUT_SEL to 0 */
+#define IMXRT_PAD_GPIO_AD_B1_00__LPUART2_CTS_B 0x00fc 0x02ec 0x0000 2 0
+#define IMXRT_PAD_GPIO_AD_B1_00__LPI2C1_SCL 0x00fc 0x02ec 0x04cc 3 1
+#define IMXRT_PAD_GPIO_AD_B1_00__WDOG1_wdog_b 0x00fc 0x02ec 0x0000 4 0
+#define IMXRT_PAD_GPIO_AD_B1_00__GPIO1_gpio_io16 0x00fc 0x02ec 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B1_00__USDHC1_usdhc_wp 0x00fc 0x02ec 0x05d8 6 2
+#define IMXRT_PAD_GPIO_AD_B1_00__KPP_kpp_row7 0x00fc 0x02ec 0x0000 7 0
+#define IMXRT_PAD_GPIO_AD_B1_00__ADC1_IN5 0x00fc 0x02ec 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B1_00__ADC2_IN5 0x00fc 0x02ec 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B1_00__CMP4_IN2 0x00fc 0x02ec 0x0000 5 0
+
+/* GPIO_AD_B1_01 */
+#define IMXRT_PAD_GPIO_AD_B1_01__USB1_usb_otg1_pwr 0x0100 0x02f0 0x0000 0 0
+#define IMXRT_PAD_GPIO_AD_B1_01__TMR3_TIMER1 0x0100 0x02f0 0x0580 1 0 /* Maybe you want to set IOMUXC_GPR_GPR6 QTIMER3_TRM1_INPUT_SEL to 0 */
+#define IMXRT_PAD_GPIO_AD_B1_01__LPUART2_RTS_B 0x0100 0x02f0 0x0000 2 0
+#define IMXRT_PAD_GPIO_AD_B1_01__LPI2C1_SDA 0x0100 0x02f0 0x04d0 3 1
+#define IMXRT_PAD_GPIO_AD_B1_01__CCM_PMIC_RDY 0x0100 0x02f0 0x03fc 4 2
+#define IMXRT_PAD_GPIO_AD_B1_01__GPIO1_gpio_io17 0x0100 0x02f0 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B1_01__USDHC1_usdhc_vselect 0x0100 0x02f0 0x0000 6 0
+#define IMXRT_PAD_GPIO_AD_B1_01__KPP_kpp_col7 0x0100 0x02f0 0x0000 7 0
+#define IMXRT_PAD_GPIO_AD_B1_01__ADC1_IN6 0x0100 0x02f0 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B1_01__ADC2_IN6 0x0100 0x02f0 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B1_01__CMP1_IN0 0x0100 0x02f0 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B1_01__CMP2_IN0 0x0100 0x02f0 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B1_01__CMP3_IN0 0x0100 0x02f0 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B1_01__CMP4_IN0 0x0100 0x02f0 0x0000 5 0
+
+/* GPIO_AD_B1_02 */
+#define IMXRT_PAD_GPIO_AD_B1_02__USB1_usb_otg1_id 0x0104 0x02f4 0x03f4 0 1
+#define IMXRT_PAD_GPIO_AD_B1_02__TMR3_TIMER2 0x0104 0x02f4 0x0584 1 1 /* Maybe you want to set IOMUXC_GPR_GPR6 QTIMER3_TRM2_INPUT_SEL to 0 */
+#define IMXRT_PAD_GPIO_AD_B1_02__LPUART2_TX 0x0104 0x02f4 0x0530 2 1
+#define IMXRT_PAD_GPIO_AD_B1_02__SPDIF_spdif_out 0x0104 0x02f4 0x0000 3 0
+#define IMXRT_PAD_GPIO_AD_B1_02__ENET_1588_EVENT2_OUT 0x0104 0x02f4 0x0000 4 0
+#define IMXRT_PAD_GPIO_AD_B1_02__GPIO1_gpio_io18 0x0104 0x02f4 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B1_02__USDHC1_usdhc_cd_b 0x0104 0x02f4 0x05d4 6 1
+#define IMXRT_PAD_GPIO_AD_B1_02__KPP_kpp_row6 0x0104 0x02f4 0x0000 7 0
+#define IMXRT_PAD_GPIO_AD_B1_02__ADC1_IN7 0x0104 0x02f4 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B1_02__ADC2_IN7 0x0104 0x02f4 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B1_02__CMP1_IN3 0x0104 0x02f4 0x0000 5 0
+
+/* GPIO_AD_B1_03 */
+#define IMXRT_PAD_GPIO_AD_B1_03__USB1_usb_otg1_oc 0x0108 0x02f8 0x05d0 0 1
+#define IMXRT_PAD_GPIO_AD_B1_03__TMR3_TIMER3 0x0108 0x02f8 0x0588 1 1 /* Maybe you want to set IOMUXC_GPR_GPR6 QTIMER3_TRM3_INPUT_SEL to 0 */
+#define IMXRT_PAD_GPIO_AD_B1_03__LPUART2_RX 0x0108 0x02f8 0x052c 2 1
+#define IMXRT_PAD_GPIO_AD_B1_03__SPDIF_spdif_in 0x0108 0x02f8 0x05c8 3 0
+#define IMXRT_PAD_GPIO_AD_B1_03__ENET_1588_EVENT2_IN 0x0108 0x02f8 0x0000 4 0
+#define IMXRT_PAD_GPIO_AD_B1_03__GPIO1_gpio_io19 0x0108 0x02f8 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B1_03__USDHC2_usdhc_cd_b 0x0108 0x02f8 0x05e0 6 0
+#define IMXRT_PAD_GPIO_AD_B1_03__KPP_kpp_col6 0x0108 0x02f8 0x0000 7 0
+#define IMXRT_PAD_GPIO_AD_B1_03__ADC1_IN8 0x0108 0x02f8 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B1_03__ADC2_IN8 0x0108 0x02f8 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B1_03__CMP2_IN3 0x0108 0x02f8 0x0000 5 0
+
+/* GPIO_AD_B1_04 */
+#define IMXRT_PAD_GPIO_AD_B1_04__FLEXSPI_FLEXSPI_B_DATA3 0x010c 0x02fc 0x04c4 0 1
+#define IMXRT_PAD_GPIO_AD_B1_04__ENET_enet_mdc 0x010c 0x02fc 0x0000 1 0
+#define IMXRT_PAD_GPIO_AD_B1_04__LPUART3_CTS_B 0x010c 0x02fc 0x0534 2 1
+#define IMXRT_PAD_GPIO_AD_B1_04__SPDIF_spdif_sr_clk 0x010c 0x02fc 0x0000 3 0
+#define IMXRT_PAD_GPIO_AD_B1_04__CSI_csi_pixclk 0x010c 0x02fc 0x0424 4 0
+#define IMXRT_PAD_GPIO_AD_B1_04__GPIO1_gpio_io20 0x010c 0x02fc 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B1_04__USDHC2_usdhc_data0 0x010c 0x02fc 0x05e8 6 1
+#define IMXRT_PAD_GPIO_AD_B1_04__KPP_kpp_row5 0x010c 0x02fc 0x0000 7 0
+#define IMXRT_PAD_GPIO_AD_B1_04__ADC1_IN9 0x010c 0x02fc 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B1_04__ADC2_IN9 0x010c 0x02fc 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B1_04__CMP3_IN3 0x010c 0x02fc 0x0000 5 0
+
+/* GPIO_AD_B1_05 */
+#define IMXRT_PAD_GPIO_AD_B1_05__FLEXSPI_FLEXSPI_B_DATA2 0x0110 0x0300 0x04c0 0 1
+#define IMXRT_PAD_GPIO_AD_B1_05__ENET_enet_mdio 0x0110 0x0300 0x0430 1 0
+#define IMXRT_PAD_GPIO_AD_B1_05__LPUART3_RTS_B 0x0110 0x0300 0x0000 2 0
+#define IMXRT_PAD_GPIO_AD_B1_05__SPDIF_spdif_out 0x0110 0x0300 0x0000 3 0
+#define IMXRT_PAD_GPIO_AD_B1_05__CSI_csi_mclk 0x0110 0x0300 0x0000 4 0
+#define IMXRT_PAD_GPIO_AD_B1_05__GPIO1_gpio_io21 0x0110 0x0300 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B1_05__USDHC2_usdhc_data1 0x0110 0x0300 0x05ec 6 1
+#define IMXRT_PAD_GPIO_AD_B1_05__KPP_kpp_col5 0x0110 0x0300 0x0000 7 0
+#define IMXRT_PAD_GPIO_AD_B1_05__ADC1_IN10 0x0110 0x0300 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B1_05__ADC2_IN10 0x0110 0x0300 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B1_05__CMP4_IN3 0x0110 0x0300 0x0000 5 0
+
+/* GPIO_AD_B1_06 */
+#define IMXRT_PAD_GPIO_AD_B1_06__FLEXSPI_FLEXSPI_B_DATA1 0x0114 0x0304 0x04bc 0 1
+#define IMXRT_PAD_GPIO_AD_B1_06__LPI2C3_SDA 0x0114 0x0304 0x04e0 1 2
+#define IMXRT_PAD_GPIO_AD_B1_06__LPUART3_TX 0x0114 0x0304 0x053c 2 0
+#define IMXRT_PAD_GPIO_AD_B1_06__SPDIF_spdif_lock 0x0114 0x0304 0x0000 3 0
+#define IMXRT_PAD_GPIO_AD_B1_06__CSI_csi_vsync 0x0114 0x0304 0x0428 4 1
+#define IMXRT_PAD_GPIO_AD_B1_06__GPIO1_gpio_io22 0x0114 0x0304 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B1_06__USDHC2_usdhc_data2 0x0114 0x0304 0x05f0 6 1
+#define IMXRT_PAD_GPIO_AD_B1_06__KPP_kpp_row4 0x0114 0x0304 0x0000 7 0
+#define IMXRT_PAD_GPIO_AD_B1_06__ADC1_IN11 0x0114 0x0304 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B1_06__ADC2_IN11 0x0114 0x0304 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B1_06__CMP1_IN1 0x0114 0x0304 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B1_06__CMP2_IN1 0x0114 0x0304 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B1_06__CMP3_IN1 0x0114 0x0304 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B1_06__CMP4_IN1 0x0114 0x0304 0x0000 5 0
+
+/* GPIO_AD_B1_07 */
+#define IMXRT_PAD_GPIO_AD_B1_07__FLEXSPI_FLEXSPI_B_DATA0 0x0118 0x0308 0x04b8 0 1
+#define IMXRT_PAD_GPIO_AD_B1_07__LPI2C3_SCL 0x0118 0x0308 0x04dc 1 2
+#define IMXRT_PAD_GPIO_AD_B1_07__LPUART3_RX 0x0118 0x0308 0x0538 2 0
+#define IMXRT_PAD_GPIO_AD_B1_07__SPDIF_spdif_ext_clk 0x0118 0x0308 0x0000 3 0
+#define IMXRT_PAD_GPIO_AD_B1_07__CSI_csi_hsync 0x0118 0x0308 0x0420 4 1
+#define IMXRT_PAD_GPIO_AD_B1_07__GPIO1_gpio_io23 0x0118 0x0308 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B1_07__USDHC2_usdhc_data3 0x0118 0x0308 0x05f4 6 1
+#define IMXRT_PAD_GPIO_AD_B1_07__KPP_kpp_col4 0x0118 0x0308 0x0000 7 0
+#define IMXRT_PAD_GPIO_AD_B1_07__ADC1_IN12 0x0118 0x0308 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B1_07__ADC2_IN12 0x0118 0x0308 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B1_07__CMP1_IN5 0x0118 0x0308 0x0000 5 0
+
+/* GPIO_AD_B1_08 */
+#define IMXRT_PAD_GPIO_AD_B1_08__FLEXSPI_FLEXSPI_A_SS1_B 0x011c 0x030c 0x0000 0 0
+#define IMXRT_PAD_GPIO_AD_B1_08__PWM4_A0 0x011c 0x030c 0x0494 1 1
+#define IMXRT_PAD_GPIO_AD_B1_08__CAN1_TX 0x011c 0x030c 0x0000 2 0
+#define IMXRT_PAD_GPIO_AD_B1_08__CCM_PMIC_RDY 0x011c 0x030c 0x03fc 3 3
+#define IMXRT_PAD_GPIO_AD_B1_08__CSI_csi_data09 0x011c 0x030c 0x041c 4 0
+#define IMXRT_PAD_GPIO_AD_B1_08__GPIO1_gpio_io24 0x011c 0x030c 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B1_08__USDHC2_usdhc_cmd 0x011c 0x030c 0x05e4 6 1
+#define IMXRT_PAD_GPIO_AD_B1_08__KPP_kpp_row3 0x011c 0x030c 0x0000 7 0
+#define IMXRT_PAD_GPIO_AD_B1_08__ADC1_IN13 0x011c 0x030c 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B1_08__ADC2_IN13 0x011c 0x030c 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B1_08__CMP2_IN5 0x011c 0x030c 0x0000 5 0
+
+/* GPIO_AD_B1_09 */
+#define IMXRT_PAD_GPIO_AD_B1_09__FLEXSPI_FLEXSPI_A_DQS 0x0120 0x0310 0x04a4 0 1
+#define IMXRT_PAD_GPIO_AD_B1_09__PWM4_A1 0x0120 0x0310 0x0498 1 1
+#define IMXRT_PAD_GPIO_AD_B1_09__CAN1_RX 0x0120 0x0310 0x044c 2 2
+#define IMXRT_PAD_GPIO_AD_B1_09__SAI1_sai_mclk 0x0120 0x0310 0x058c 3 1
+#define IMXRT_PAD_GPIO_AD_B1_09__CSI_csi_data08 0x0120 0x0310 0x0418 4 0
+#define IMXRT_PAD_GPIO_AD_B1_09__GPIO1_gpio_io25 0x0120 0x0310 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B1_09__USDHC2_usdhc_clk 0x0120 0x0310 0x05dc 6 1
+#define IMXRT_PAD_GPIO_AD_B1_09__KPP_kpp_col3 0x0120 0x0310 0x0000 7 0
+#define IMXRT_PAD_GPIO_AD_B1_09__ADC1_IN14 0x0120 0x0310 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B1_09__ADC2_IN14 0x0120 0x0310 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B1_09__CMP3_IN5 0x0120 0x0310 0x0000 5 0
+
+/* GPIO_AD_B1_10 */
+#define IMXRT_PAD_GPIO_AD_B1_10__FLEXSPI_FLEXSPI_A_DATA3 0x0124 0x0314 0x04b4 0 1
+#define IMXRT_PAD_GPIO_AD_B1_10__WDOG1_wdog_b 0x0124 0x0314 0x0000 1 0
+#define IMXRT_PAD_GPIO_AD_B1_10__LPUART8_TX 0x0124 0x0314 0x0564 2 1
+#define IMXRT_PAD_GPIO_AD_B1_10__SAI1_sai_rx_sync 0x0124 0x0314 0x05a4 3 1
+#define IMXRT_PAD_GPIO_AD_B1_10__CSI_csi_data07 0x0124 0x0314 0x0414 4 0
+#define IMXRT_PAD_GPIO_AD_B1_10__GPIO1_gpio_io26 0x0124 0x0314 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B1_10__USDHC2_usdhc_wp 0x0124 0x0314 0x0608 6 1
+#define IMXRT_PAD_GPIO_AD_B1_10__KPP_kpp_row2 0x0124 0x0314 0x0000 7 0
+#define IMXRT_PAD_GPIO_AD_B1_10__ADC1_IN15 0x0124 0x0314 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B1_10__ADC2_IN15 0x0124 0x0314 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B1_10__CMP4_IN5 0x0124 0x0314 0x0000 5 0
+
+/* GPIO_AD_B1_11 */
+#define IMXRT_PAD_GPIO_AD_B1_11__FLEXSPI_FLEXSPI_A_DATA2 0x0128 0x0318 0x04b0 0 1
+#define IMXRT_PAD_GPIO_AD_B1_11__EWM_EWM_OUT_B 0x0128 0x0318 0x0000 1 0
+#define IMXRT_PAD_GPIO_AD_B1_11__LPUART8_RX 0x0128 0x0318 0x0560 2 1
+#define IMXRT_PAD_GPIO_AD_B1_11__SAI1_sai_rx_bclk 0x0128 0x0318 0x0590 3 1
+#define IMXRT_PAD_GPIO_AD_B1_11__CSI_csi_data06 0x0128 0x0318 0x0410 4 0
+#define IMXRT_PAD_GPIO_AD_B1_11__GPIO1_gpio_io27 0x0128 0x0318 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B1_11__USDHC2_usdhc_reset_b 0x0128 0x0318 0x0000 6 0
+#define IMXRT_PAD_GPIO_AD_B1_11__KPP_kpp_col2 0x0128 0x0318 0x0000 7 0
+#define IMXRT_PAD_GPIO_AD_B1_11__ADC1_IN0 0x0128 0x0318 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B1_11__ADC2_IN0 0x0128 0x0318 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B1_11__CMP1_IN6 0x0128 0x0318 0x0000 5 0
+
+/* GPIO_AD_B1_12 */
+#define IMXRT_PAD_GPIO_AD_B1_12__FLEXSPI_FLEXSPI_A_DATA1 0x012c 0x031c 0x04ac 0 1
+#define IMXRT_PAD_GPIO_AD_B1_12__CMP1_OUT 0x012c 0x031c 0x0000 1 0
+#define IMXRT_PAD_GPIO_AD_B1_12__LPSPI3_PCS0 0x012c 0x031c 0x050c 2 1
+#define IMXRT_PAD_GPIO_AD_B1_12__SAI1_sai_rx_data0 0x012c 0x031c 0x0594 3 1
+#define IMXRT_PAD_GPIO_AD_B1_12__CSI_csi_data05 0x012c 0x031c 0x040c 4 0
+#define IMXRT_PAD_GPIO_AD_B1_12__GPIO1_gpio_io28 0x012c 0x031c 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B1_12__USDHC2_usdhc_data4 0x012c 0x031c 0x05f8 6 1
+#define IMXRT_PAD_GPIO_AD_B1_12__KPP_kpp_row1 0x012c 0x031c 0x0000 7 0
+#define IMXRT_PAD_GPIO_AD_B1_12__ADC2_IN1 0x012c 0x031c 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B1_12__CMP2_IN6 0x012c 0x031c 0x0000 5 0
+
+/* GPIO_AD_B1_13 */
+#define IMXRT_PAD_GPIO_AD_B1_13__FLEXSPI_FLEXSPI_A_DATA0 0x0130 0x0320 0x04a8 0 1
+#define IMXRT_PAD_GPIO_AD_B1_13__CMP2_OUT 0x0130 0x0320 0x0000 1 0
+#define IMXRT_PAD_GPIO_AD_B1_13__LPSPI3_SDI 0x0130 0x0320 0x0514 2 1
+#define IMXRT_PAD_GPIO_AD_B1_13__SAI1_sai_tx_data0 0x0130 0x0320 0x0000 3 0
+#define IMXRT_PAD_GPIO_AD_B1_13__CSI_csi_data04 0x0130 0x0320 0x0408 4 0
+#define IMXRT_PAD_GPIO_AD_B1_13__GPIO1_gpio_io29 0x0130 0x0320 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B1_13__USDHC2_usdhc_data5 0x0130 0x0320 0x05fc 6 1
+#define IMXRT_PAD_GPIO_AD_B1_13__KPP_kpp_col1 0x0130 0x0320 0x0000 7 0
+#define IMXRT_PAD_GPIO_AD_B1_13__ADC2_IN2 0x0130 0x0320 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B1_13__CMP3_IN6 0x0130 0x0320 0x0000 5 0
+
+/* GPIO_AD_B1_14 */
+#define IMXRT_PAD_GPIO_AD_B1_14__FLEXSPI_FLEXSPI_A_SCLK 0x0134 0x0324 0x04c8 0 1
+#define IMXRT_PAD_GPIO_AD_B1_14__CMP3_OUT 0x0134 0x0324 0x0000 1 0
+#define IMXRT_PAD_GPIO_AD_B1_14__LPSPI3_SDO 0x0134 0x0324 0x0518 2 1
+#define IMXRT_PAD_GPIO_AD_B1_14__SAI1_sai_tx_bclk 0x0134 0x0324 0x05a8 3 1
+#define IMXRT_PAD_GPIO_AD_B1_14__CSI_csi_data03 0x0134 0x0324 0x0404 4 0
+#define IMXRT_PAD_GPIO_AD_B1_14__GPIO1_gpio_io30 0x0134 0x0324 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B1_14__USDHC2_usdhc_data6 0x0134 0x0324 0x0600 6 1
+#define IMXRT_PAD_GPIO_AD_B1_14__KPP_kpp_row0 0x0134 0x0324 0x0000 7 0
+#define IMXRT_PAD_GPIO_AD_B1_14__ADC2_IN3 0x0134 0x0324 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B1_14__CMP4_IN6 0x0134 0x0324 0x0000 5 0
+
+/* GPIO_AD_B1_15 */
+#define IMXRT_PAD_GPIO_AD_B1_15__FLEXSPI_FLEXSPI_A_SS0_B 0x0138 0x0328 0x0000 0 0
+#define IMXRT_PAD_GPIO_AD_B1_15__CMP4_OUT 0x0138 0x0328 0x0000 1 0
+#define IMXRT_PAD_GPIO_AD_B1_15__LPSPI3_SCK 0x0138 0x0328 0x0000 2 0
+#define IMXRT_PAD_GPIO_AD_B1_15__SAI1_sai_tx_sync 0x0138 0x0328 0x05ac 3 1
+#define IMXRT_PAD_GPIO_AD_B1_15__CSI_csi_data02 0x0138 0x0328 0x0400 4 0
+#define IMXRT_PAD_GPIO_AD_B1_15__GPIO1_gpio_io31 0x0138 0x0328 0x0000 5 0
+#define IMXRT_PAD_GPIO_AD_B1_15__USDHC2_usdhc_data7 0x0138 0x0328 0x0604 6 1
+#define IMXRT_PAD_GPIO_AD_B1_15__KPP_kpp_col0 0x0138 0x0328 0x0000 7 0
+#define IMXRT_PAD_GPIO_AD_B1_15__ADC2_IN4 0x0138 0x0328 0x0000 5 0
+
+/* GPIO_B0_00 */
+#define IMXRT_PAD_GPIO_B0_00__LCDIF_lcdif_clk 0x013c 0x032c 0x0000 0 0
+#define IMXRT_PAD_GPIO_B0_00__TMR1_TIMER0 0x013c 0x032c 0x0000 1 0 /* Maybe you want to set IOMUXC_GPR_GPR6 QTIMER1_TRM0_INPUT_SEL to 0 */
+#define IMXRT_PAD_GPIO_B0_00__MQS_RIGHT 0x013c 0x032c 0x0000 2 0
+#define IMXRT_PAD_GPIO_B0_00__LPSPI4_PCS0 0x013c 0x032c 0x051c 3 0
+#define IMXRT_PAD_GPIO_B0_00__FLEXIO2_IO00 0x013c 0x032c 0x0000 4 0
+#define IMXRT_PAD_GPIO_B0_00__GPIO2_gpio_io00 0x013c 0x032c 0x0000 5 0
+#define IMXRT_PAD_GPIO_B0_00__SEMC_CSX1 0x013c 0x032c 0x0000 6 0
+
+/* GPIO_B0_01 */
+#define IMXRT_PAD_GPIO_B0_01__LCDIF_lcdif_enable 0x0140 0x0330 0x0000 0 0
+#define IMXRT_PAD_GPIO_B0_01__TMR1_TIMER1 0x0140 0x0330 0x0000 1 0 /* Maybe you want to set IOMUXC_GPR_GPR6 QTIMER1_TRM1_INPUT_SEL to 0 */
+#define IMXRT_PAD_GPIO_B0_01__MQS_LEFT 0x0140 0x0330 0x0000 2 0
+#define IMXRT_PAD_GPIO_B0_01__LPSPI4_SDI 0x0140 0x0330 0x0524 3 0
+#define IMXRT_PAD_GPIO_B0_01__FLEXIO2_IO01 0x0140 0x0330 0x0000 4 0
+#define IMXRT_PAD_GPIO_B0_01__GPIO2_gpio_io01 0x0140 0x0330 0x0000 5 0
+#define IMXRT_PAD_GPIO_B0_01__SEMC_CSX2 0x0140 0x0330 0x0000 6 0
+
+/* GPIO_B0_02 */
+#define IMXRT_PAD_GPIO_B0_02__LCDIF_lcdif_hsync 0x0144 0x0334 0x0000 0 0
+#define IMXRT_PAD_GPIO_B0_02__TMR1_TIMER2 0x0144 0x0334 0x0000 1 0 /* Maybe you want to set IOMUXC_GPR_GPR6 QTIMER1_TRM2_INPUT_SEL to 0 */
+#define IMXRT_PAD_GPIO_B0_02__CAN1_TX 0x0144 0x0334 0x0000 2 0
+#define IMXRT_PAD_GPIO_B0_02__LPSPI4_SDO 0x0144 0x0334 0x0528 3 0
+#define IMXRT_PAD_GPIO_B0_02__FLEXIO2_IO02 0x0144 0x0334 0x0000 4 0
+#define IMXRT_PAD_GPIO_B0_02__GPIO2_gpio_io02 0x0144 0x0334 0x0000 5 0
+#define IMXRT_PAD_GPIO_B0_02__SEMC_CSX3 0x0144 0x0334 0x0000 6 0
+
+/* GPIO_B0_03 */
+#define IMXRT_PAD_GPIO_B0_03__LCDIF_lcdif_vsync 0x0148 0x0338 0x0000 0 0
+#define IMXRT_PAD_GPIO_B0_03__TMR2_TIMER0 0x0148 0x0338 0x056c 1 1 /* Maybe you want to set IOMUXC_GPR_GPR6 QTIMER2_TRM0_INPUT_SEL to 0 */
+#define IMXRT_PAD_GPIO_B0_03__CAN1_RX 0x0148 0x0338 0x044c 2 3
+#define IMXRT_PAD_GPIO_B0_03__LPSPI4_SCK 0x0148 0x0338 0x0520 3 0
+#define IMXRT_PAD_GPIO_B0_03__FLEXIO2_IO03 0x0148 0x0338 0x0000 4 0
+#define IMXRT_PAD_GPIO_B0_03__GPIO2_gpio_io03 0x0148 0x0338 0x0000 5 0
+#define IMXRT_PAD_GPIO_B0_03__WDOG2_wdog_rst_b_deb 0x0148 0x0338 0x0000 6 0
+
+/* GPIO_B0_04 */
+#define IMXRT_PAD_GPIO_B0_04__LCDIF_lcdif_data00 0x014c 0x033c 0x0000 0 0
+#define IMXRT_PAD_GPIO_B0_04__TMR2_TIMER1 0x014c 0x033c 0x0570 1 1 /* Maybe you want to set IOMUXC_GPR_GPR6 QTIMER2_TRM1_INPUT_SEL to 0 */
+#define IMXRT_PAD_GPIO_B0_04__LPI2C2_SCL 0x014c 0x033c 0x04d4 2 1
+#define IMXRT_PAD_GPIO_B0_04__ARM_TRACE0 0x014c 0x033c 0x0000 3 0
+#define IMXRT_PAD_GPIO_B0_04__FLEXIO2_IO04 0x014c 0x033c 0x0000 4 0
+#define IMXRT_PAD_GPIO_B0_04__GPIO2_gpio_io04 0x014c 0x033c 0x0000 5 0
+#define IMXRT_PAD_GPIO_B0_04__SRC_BOOT_CFG0 0x014c 0x033c 0x0000 6 0
+
+/* GPIO_B0_05 */
+#define IMXRT_PAD_GPIO_B0_05__LCDIF_lcdif_data01 0x0150 0x0340 0x0000 0 0
+#define IMXRT_PAD_GPIO_B0_05__TMR2_TIMER2 0x0150 0x0340 0x0574 1 1 /* Maybe you want to set IOMUXC_GPR_GPR6 QTIMER2_TRM2_INPUT_SEL to 0 */
+#define IMXRT_PAD_GPIO_B0_05__LPI2C2_SDA 0x0150 0x0340 0x04d8 2 1
+#define IMXRT_PAD_GPIO_B0_05__ARM_TRACE1 0x0150 0x0340 0x0000 3 0
+#define IMXRT_PAD_GPIO_B0_05__FLEXIO2_IO05 0x0150 0x0340 0x0000 4 0
+#define IMXRT_PAD_GPIO_B0_05__GPIO2_gpio_io05 0x0150 0x0340 0x0000 5 0
+#define IMXRT_PAD_GPIO_B0_05__SRC_BOOT_CFG1 0x0150 0x0340 0x0000 6 0
+
+/* GPIO_B0_06 */
+#define IMXRT_PAD_GPIO_B0_06__LCDIF_lcdif_data02 0x0154 0x0344 0x0000 0 0
+#define IMXRT_PAD_GPIO_B0_06__TMR3_TIMER0 0x0154 0x0344 0x057c 1 2 /* Maybe you want to set IOMUXC_GPR_GPR6 QTIMER3_TRM0_INPUT_SEL to 0 */
+#define IMXRT_PAD_GPIO_B0_06__PWM2_A0 0x0154 0x0344 0x0478 2 1
+#define IMXRT_PAD_GPIO_B0_06__ARM_TRACE2 0x0154 0x0344 0x0000 3 0
+#define IMXRT_PAD_GPIO_B0_06__FLEXIO2_IO06 0x0154 0x0344 0x0000 4 0
+#define IMXRT_PAD_GPIO_B0_06__GPIO2_gpio_io06 0x0154 0x0344 0x0000 5 0
+#define IMXRT_PAD_GPIO_B0_06__SRC_BOOT_CFG2 0x0154 0x0344 0x0000 6 0
+
+/* GPIO_B0_07 */
+#define IMXRT_PAD_GPIO_B0_07__LCDIF_lcdif_data03 0x0158 0x0348 0x0000 0 0
+#define IMXRT_PAD_GPIO_B0_07__TMR3_TIMER1 0x0158 0x0348 0x0580 1 2 /* Maybe you want to set IOMUXC_GPR_GPR6 QTIMER3_TRM1_INPUT_SEL to 0 */
+#define IMXRT_PAD_GPIO_B0_07__PWM2_B0 0x0158 0x0348 0x0488 2 1
+#define IMXRT_PAD_GPIO_B0_07__ARM_TRACE3 0x0158 0x0348 0x0000 3 0
+#define IMXRT_PAD_GPIO_B0_07__FLEXIO2_IO07 0x0158 0x0348 0x0000 4 0
+#define IMXRT_PAD_GPIO_B0_07__GPIO2_gpio_io07 0x0158 0x0348 0x0000 5 0
+#define IMXRT_PAD_GPIO_B0_07__SRC_BOOT_CFG3 0x0158 0x0348 0x0000 6 0
+
+/* GPIO_B0_08 */
+#define IMXRT_PAD_GPIO_B0_08__LCDIF_lcdif_data04 0x015c 0x034c 0x0000 0 0
+#define IMXRT_PAD_GPIO_B0_08__TMR3_TIMER2 0x015c 0x034c 0x0584 1 2 /* Maybe you want to set IOMUXC_GPR_GPR6 QTIMER3_TRM2_INPUT_SEL to 0 */
+#define IMXRT_PAD_GPIO_B0_08__PWM2_A1 0x015c 0x034c 0x047c 2 1
+#define IMXRT_PAD_GPIO_B0_08__LPUART3_TX 0x015c 0x034c 0x053c 3 2
+#define IMXRT_PAD_GPIO_B0_08__FLEXIO2_IO08 0x015c 0x034c 0x0000 4 0
+#define IMXRT_PAD_GPIO_B0_08__GPIO2_gpio_io08 0x015c 0x034c 0x0000 5 0
+#define IMXRT_PAD_GPIO_B0_08__SRC_BOOT_CFG4 0x015c 0x034c 0x0000 6 0
+
+/* GPIO_B0_09 */
+#define IMXRT_PAD_GPIO_B0_09__LCDIF_lcdif_data05 0x0160 0x0350 0x0000 0 0
+#define IMXRT_PAD_GPIO_B0_09__TMR4_TIMER0 0x0160 0x0350 0x0000 1 0 /* Maybe you want to set IOMUXC_GPR_GPR6 QTIMER4_TRM0_INPUT_SEL to 0 */
+#define IMXRT_PAD_GPIO_B0_09__PWM2_B1 0x0160 0x0350 0x048c 2 1
+#define IMXRT_PAD_GPIO_B0_09__LPUART3_RX 0x0160 0x0350 0x0538 3 2
+#define IMXRT_PAD_GPIO_B0_09__FLEXIO2_IO09 0x0160 0x0350 0x0000 4 0
+#define IMXRT_PAD_GPIO_B0_09__GPIO2_gpio_io09 0x0160 0x0350 0x0000 5 0
+#define IMXRT_PAD_GPIO_B0_09__SRC_BOOT_CFG5 0x0160 0x0350 0x0000 6 0
+
+/* GPIO_B0_10 */
+#define IMXRT_PAD_GPIO_B0_10__LCDIF_lcdif_data06 0x0164 0x0354 0x0000 0 0
+#define IMXRT_PAD_GPIO_B0_10__TMR4_TIMER1 0x0164 0x0354 0x0000 1 0 /* Maybe you want to set IOMUXC_GPR_GPR6 QTIMER4_TRM1_INPUT_SEL to 0 */
+#define IMXRT_PAD_GPIO_B0_10__PWM2_A2 0x0164 0x0354 0x0480 2 1
+#define IMXRT_PAD_GPIO_B0_10__SAI1_sai_tx_data3 0x0164 0x0354 0x0598 3 1
+#define IMXRT_PAD_GPIO_B0_10__FLEXIO2_IO10 0x0164 0x0354 0x0000 4 0
+#define IMXRT_PAD_GPIO_B0_10__GPIO2_gpio_io10 0x0164 0x0354 0x0000 5 0
+#define IMXRT_PAD_GPIO_B0_10__SRC_BOOT_CFG6 0x0164 0x0354 0x0000 6 0
+
+/* GPIO_B0_11 */
+#define IMXRT_PAD_GPIO_B0_11__LCDIF_lcdif_data07 0x0168 0x0358 0x0000 0 0
+#define IMXRT_PAD_GPIO_B0_11__TMR4_TIMER2 0x0168 0x0358 0x0000 1 0 /* Maybe you want to set IOMUXC_GPR_GPR6 QTIMER4_TRM2_INPUT_SEL to 0 */
+#define IMXRT_PAD_GPIO_B0_11__PWM2_B2 0x0168 0x0358 0x0490 2 1
+#define IMXRT_PAD_GPIO_B0_11__SAI1_sai_tx_data2 0x0168 0x0358 0x059c 3 1
+#define IMXRT_PAD_GPIO_B0_11__FLEXIO2_IO11 0x0168 0x0358 0x0000 4 0
+#define IMXRT_PAD_GPIO_B0_11__GPIO2_gpio_io11 0x0168 0x0358 0x0000 5 0
+#define IMXRT_PAD_GPIO_B0_11__SRC_BOOT_CFG7 0x0168 0x0358 0x0000 6 0
+
+/* GPIO_B0_12 */
+#define IMXRT_PAD_GPIO_B0_12__LCDIF_lcdif_data08 0x016c 0x035c 0x0000 0 0
+#define IMXRT_PAD_GPIO_B0_12__XBARA1_OUT10 0x016c 0x035c 0x0000 1 0 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_10 to 0x1 */
+#define IMXRT_PAD_GPIO_B0_12__XBARA1_IN10 0x016c 0x035c 0x0000 1 0 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_10 to 0 */
+#define IMXRT_PAD_GPIO_B0_12__ARM_arm_trace_clk 0x016c 0x035c 0x0000 2 0
+#define IMXRT_PAD_GPIO_B0_12__SAI1_sai_tx_data1 0x016c 0x035c 0x05a0 3 1
+#define IMXRT_PAD_GPIO_B0_12__FLEXIO2_IO12 0x016c 0x035c 0x0000 4 0
+#define IMXRT_PAD_GPIO_B0_12__GPIO2_gpio_io12 0x016c 0x035c 0x0000 5 0
+#define IMXRT_PAD_GPIO_B0_12__SRC_BOOT_CFG8 0x016c 0x035c 0x0000 6 0
+
+/* GPIO_B0_13 */
+#define IMXRT_PAD_GPIO_B0_13__LCDIF_lcdif_data09 0x0170 0x0360 0x0000 0 0
+#define IMXRT_PAD_GPIO_B0_13__XBARA1_OUT11 0x0170 0x0360 0x0000 1 0 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_11 to 0x1 */
+#define IMXRT_PAD_GPIO_B0_13__XBARA1_IN11 0x0170 0x0360 0x0000 1 0 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_11 to 0 */
+#define IMXRT_PAD_GPIO_B0_13__ARM_arm_trace_swo 0x0170 0x0360 0x0000 2 0
+#define IMXRT_PAD_GPIO_B0_13__SAI1_sai_mclk 0x0170 0x0360 0x058c 3 2
+#define IMXRT_PAD_GPIO_B0_13__FLEXIO2_IO13 0x0170 0x0360 0x0000 4 0
+#define IMXRT_PAD_GPIO_B0_13__GPIO2_gpio_io13 0x0170 0x0360 0x0000 5 0
+#define IMXRT_PAD_GPIO_B0_13__SRC_BOOT_CFG9 0x0170 0x0360 0x0000 6 0
+
+/* GPIO_B0_14 */
+#define IMXRT_PAD_GPIO_B0_14__LCDIF_lcdif_data10 0x0174 0x0364 0x0000 0 0
+#define IMXRT_PAD_GPIO_B0_14__XBARA1_OUT12 0x0174 0x0364 0x0000 1 0 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_12 to 0x1 */
+#define IMXRT_PAD_GPIO_B0_14__XBARA1_IN12 0x0174 0x0364 0x0000 1 0 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_12 to 0 */
+#define IMXRT_PAD_GPIO_B0_14__ARM_arm_cm7_txev 0x0174 0x0364 0x0000 2 0
+#define IMXRT_PAD_GPIO_B0_14__SAI1_sai_rx_sync 0x0174 0x0364 0x05a4 3 2
+#define IMXRT_PAD_GPIO_B0_14__FLEXIO2_IO14 0x0174 0x0364 0x0000 4 0
+#define IMXRT_PAD_GPIO_B0_14__GPIO2_gpio_io14 0x0174 0x0364 0x0000 5 0
+#define IMXRT_PAD_GPIO_B0_14__SRC_BOOT_CFG10 0x0174 0x0364 0x0000 6 0
+
+/* GPIO_B0_15 */
+#define IMXRT_PAD_GPIO_B0_15__LCDIF_lcdif_data11 0x0178 0x0368 0x0000 0 0
+#define IMXRT_PAD_GPIO_B0_15__XBARA1_OUT13 0x0178 0x0368 0x0000 1 0 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_13 to 0x1 */
+#define IMXRT_PAD_GPIO_B0_15__XBARA1_IN13 0x0178 0x0368 0x0000 1 0 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_13 to 0 */
+#define IMXRT_PAD_GPIO_B0_15__ARM_arm_cm7_rxev 0x0178 0x0368 0x0000 2 0
+#define IMXRT_PAD_GPIO_B0_15__SAI1_sai_rx_bclk 0x0178 0x0368 0x0590 3 2
+#define IMXRT_PAD_GPIO_B0_15__FLEXIO2_IO15 0x0178 0x0368 0x0000 4 0
+#define IMXRT_PAD_GPIO_B0_15__GPIO2_gpio_io15 0x0178 0x0368 0x0000 5 0
+#define IMXRT_PAD_GPIO_B0_15__SRC_BOOT_CFG11 0x0178 0x0368 0x0000 6 0
+
+/* GPIO_B1_00 */
+#define IMXRT_PAD_GPIO_B1_00__LCDIF_lcdif_data12 0x017c 0x036c 0x0000 0 0
+#define IMXRT_PAD_GPIO_B1_00__XBARA1_OUT14 0x017c 0x036c 0x0644 1 1 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_14 to 0x1 */
+#define IMXRT_PAD_GPIO_B1_00__XBARA1_IN14 0x017c 0x036c 0x0644 1 1 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_14 to 0 */
+#define IMXRT_PAD_GPIO_B1_00__LPUART4_TX 0x017c 0x036c 0x0544 2 2
+#define IMXRT_PAD_GPIO_B1_00__SAI1_sai_rx_data0 0x017c 0x036c 0x0594 3 2
+#define IMXRT_PAD_GPIO_B1_00__FLEXIO2_IO16 0x017c 0x036c 0x0000 4 0
+#define IMXRT_PAD_GPIO_B1_00__GPIO2_gpio_io16 0x017c 0x036c 0x0000 5 0
+#define IMXRT_PAD_GPIO_B1_00__PWM1_A3 0x017c 0x036c 0x0454 6 4
+
+/* GPIO_B1_01 */
+#define IMXRT_PAD_GPIO_B1_01__LCDIF_lcdif_data13 0x0180 0x0370 0x0000 0 0
+#define IMXRT_PAD_GPIO_B1_01__XBARA1_OUT15 0x0180 0x0370 0x0648 1 1 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_15 to 0x1 */
+#define IMXRT_PAD_GPIO_B1_01__XBARA1_IN15 0x0180 0x0370 0x0648 1 1 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_15 to 0 */
+#define IMXRT_PAD_GPIO_B1_01__LPUART4_RX 0x0180 0x0370 0x0540 2 2
+#define IMXRT_PAD_GPIO_B1_01__SAI1_sai_tx_data0 0x0180 0x0370 0x0000 3 0
+#define IMXRT_PAD_GPIO_B1_01__FLEXIO2_IO17 0x0180 0x0370 0x0000 4 0
+#define IMXRT_PAD_GPIO_B1_01__GPIO2_gpio_io17 0x0180 0x0370 0x0000 5 0
+#define IMXRT_PAD_GPIO_B1_01__PWM1_B3 0x0180 0x0370 0x0464 6 4
+
+/* GPIO_B1_02 */
+#define IMXRT_PAD_GPIO_B1_02__LCDIF_lcdif_data14 0x0184 0x0374 0x0000 0 0
+#define IMXRT_PAD_GPIO_B1_02__XBARA1_OUT16 0x0184 0x0374 0x064c 1 1 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_16 to 0x1 */
+#define IMXRT_PAD_GPIO_B1_02__XBARA1_IN16 0x0184 0x0374 0x064c 1 1 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_16 to 0 */
+#define IMXRT_PAD_GPIO_B1_02__LPSPI4_PCS2 0x0184 0x0374 0x0000 2 0
+#define IMXRT_PAD_GPIO_B1_02__SAI1_sai_tx_bclk 0x0184 0x0374 0x05a8 3 2
+#define IMXRT_PAD_GPIO_B1_02__FLEXIO2_IO18 0x0184 0x0374 0x0000 4 0
+#define IMXRT_PAD_GPIO_B1_02__GPIO2_gpio_io18 0x0184 0x0374 0x0000 5 0
+#define IMXRT_PAD_GPIO_B1_02__PWM2_A3 0x0184 0x0374 0x0474 6 4
+
+/* GPIO_B1_03 */
+#define IMXRT_PAD_GPIO_B1_03__LCDIF_lcdif_data15 0x0188 0x0378 0x0000 0 0
+#define IMXRT_PAD_GPIO_B1_03__XBARA1_OUT17 0x0188 0x0378 0x062c 1 3 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_17 to 0x1 */
+#define IMXRT_PAD_GPIO_B1_03__XBARA1_IN17 0x0188 0x0378 0x062c 1 3 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_17 to 0 */
+#define IMXRT_PAD_GPIO_B1_03__LPSPI4_PCS1 0x0188 0x0378 0x0000 2 0
+#define IMXRT_PAD_GPIO_B1_03__SAI1_sai_tx_sync 0x0188 0x0378 0x05ac 3 2
+#define IMXRT_PAD_GPIO_B1_03__FLEXIO2_IO19 0x0188 0x0378 0x0000 4 0
+#define IMXRT_PAD_GPIO_B1_03__GPIO2_gpio_io19 0x0188 0x0378 0x0000 5 0
+#define IMXRT_PAD_GPIO_B1_03__PWM2_B3 0x0188 0x0378 0x0484 6 3
+
+/* GPIO_B1_04 */
+#define IMXRT_PAD_GPIO_B1_04__LCDIF_lcdif_data16 0x018c 0x037c 0x0000 0 0
+#define IMXRT_PAD_GPIO_B1_04__LPSPI4_PCS0 0x018c 0x037c 0x051c 1 1
+#define IMXRT_PAD_GPIO_B1_04__CSI_csi_data15 0x018c 0x037c 0x0000 2 0
+#define IMXRT_PAD_GPIO_B1_04__ENET_enet_rx_data0 0x018c 0x037c 0x0434 3 1
+#define IMXRT_PAD_GPIO_B1_04__FLEXIO2_IO20 0x018c 0x037c 0x0000 4 0
+#define IMXRT_PAD_GPIO_B1_04__GPIO2_gpio_io20 0x018c 0x037c 0x0000 5 0
+
+/* GPIO_B1_05 */
+#define IMXRT_PAD_GPIO_B1_05__LCDIF_lcdif_data17 0x0190 0x0380 0x0000 0 0
+#define IMXRT_PAD_GPIO_B1_05__LPSPI4_SDI 0x0190 0x0380 0x0524 1 1
+#define IMXRT_PAD_GPIO_B1_05__CSI_csi_data14 0x0190 0x0380 0x0000 2 0
+#define IMXRT_PAD_GPIO_B1_05__ENET_enet_rx_data1 0x0190 0x0380 0x0438 3 1
+#define IMXRT_PAD_GPIO_B1_05__FLEXIO2_IO21 0x0190 0x0380 0x0000 4 0
+#define IMXRT_PAD_GPIO_B1_05__GPIO2_gpio_io21 0x0190 0x0380 0x0000 5 0
+
+/* GPIO_B1_06 */
+#define IMXRT_PAD_GPIO_B1_06__LCDIF_lcdif_data18 0x0194 0x0384 0x0000 0 0
+#define IMXRT_PAD_GPIO_B1_06__LPSPI4_SDO 0x0194 0x0384 0x0528 1 1
+#define IMXRT_PAD_GPIO_B1_06__CSI_csi_data13 0x0194 0x0384 0x0000 2 0
+#define IMXRT_PAD_GPIO_B1_06__ENET_enet_rx_en 0x0194 0x0384 0x043c 3 1
+#define IMXRT_PAD_GPIO_B1_06__FLEXIO2_IO22 0x0194 0x0384 0x0000 4 0
+#define IMXRT_PAD_GPIO_B1_06__GPIO2_gpio_io22 0x0194 0x0384 0x0000 5 0
+
+/* GPIO_B1_07 */
+#define IMXRT_PAD_GPIO_B1_07__LCDIF_lcdif_data19 0x0198 0x0388 0x0000 0 0
+#define IMXRT_PAD_GPIO_B1_07__LPSPI4_SCK 0x0198 0x0388 0x0520 1 1
+#define IMXRT_PAD_GPIO_B1_07__CSI_csi_data12 0x0198 0x0388 0x0000 2 0
+#define IMXRT_PAD_GPIO_B1_07__ENET_enet_tx_data0 0x0198 0x0388 0x0000 3 0
+#define IMXRT_PAD_GPIO_B1_07__FLEXIO2_IO23 0x0198 0x0388 0x0000 4 0
+#define IMXRT_PAD_GPIO_B1_07__GPIO2_gpio_io23 0x0198 0x0388 0x0000 5 0
+
+/* GPIO_B1_08 */
+#define IMXRT_PAD_GPIO_B1_08__LCDIF_lcdif_data20 0x019c 0x038c 0x0000 0 0
+#define IMXRT_PAD_GPIO_B1_08__TMR1_TIMER3 0x019c 0x038c 0x0000 1 0 /* Maybe you want to set IOMUXC_GPR_GPR6 QTIMER1_TRM3_INPUT_SEL to 0 */
+#define IMXRT_PAD_GPIO_B1_08__CSI_csi_data11 0x019c 0x038c 0x0000 2 0
+#define IMXRT_PAD_GPIO_B1_08__ENET_enet_tx_data1 0x019c 0x038c 0x0000 3 0
+#define IMXRT_PAD_GPIO_B1_08__FLEXIO2_IO24 0x019c 0x038c 0x0000 4 0
+#define IMXRT_PAD_GPIO_B1_08__GPIO2_gpio_io24 0x019c 0x038c 0x0000 5 0
+#define IMXRT_PAD_GPIO_B1_08__CAN2_TX 0x019c 0x038c 0x0000 6 0
+
+/* GPIO_B1_09 */
+#define IMXRT_PAD_GPIO_B1_09__LCDIF_lcdif_data21 0x01a0 0x0390 0x0000 0 0
+#define IMXRT_PAD_GPIO_B1_09__TMR2_TIMER3 0x01a0 0x0390 0x0578 1 1 /* Maybe you want to set IOMUXC_GPR_GPR6 QTIMER2_TRM3_INPUT_SEL to 0 */
+#define IMXRT_PAD_GPIO_B1_09__CSI_csi_data10 0x01a0 0x0390 0x0000 2 0
+#define IMXRT_PAD_GPIO_B1_09__ENET_enet_tx_en 0x01a0 0x0390 0x0000 3 0
+#define IMXRT_PAD_GPIO_B1_09__FLEXIO2_IO25 0x01a0 0x0390 0x0000 4 0
+#define IMXRT_PAD_GPIO_B1_09__GPIO2_gpio_io25 0x01a0 0x0390 0x0000 5 0
+#define IMXRT_PAD_GPIO_B1_09__CAN2_RX 0x01a0 0x0390 0x0450 6 3
+
+/* GPIO_B1_10 */
+#define IMXRT_PAD_GPIO_B1_10__LCDIF_lcdif_data22 0x01a4 0x0394 0x0000 0 0
+#define IMXRT_PAD_GPIO_B1_10__TMR3_TIMER3 0x01a4 0x0394 0x0588 1 2 /* Maybe you want to set IOMUXC_GPR_GPR6 QTIMER3_TRM3_INPUT_SEL to 0 */
+#define IMXRT_PAD_GPIO_B1_10__CSI_csi_data00 0x01a4 0x0394 0x0000 2 0
+#define IMXRT_PAD_GPIO_B1_10__ENET_enet_tx_clk 0x01a4 0x0394 0x0448 3 1
+#define IMXRT_PAD_GPIO_B1_10__FLEXIO2_IO26 0x01a4 0x0394 0x0000 4 0
+#define IMXRT_PAD_GPIO_B1_10__GPIO2_gpio_io26 0x01a4 0x0394 0x0000 5 0
+#define IMXRT_PAD_GPIO_B1_10__ENET_enet_ref_clk 0x01a4 0x0394 0x042c 6 1
+
+/* GPIO_B1_11 */
+#define IMXRT_PAD_GPIO_B1_11__LCDIF_lcdif_data23 0x01a8 0x0398 0x0000 0 0
+#define IMXRT_PAD_GPIO_B1_11__TMR4_TIMER3 0x01a8 0x0398 0x0000 1 0 /* Maybe you want to set IOMUXC_GPR_GPR6 QTIMER4_TRM3_INPUT_SEL to 0 */
+#define IMXRT_PAD_GPIO_B1_11__CSI_csi_data01 0x01a8 0x0398 0x0000 2 0
+#define IMXRT_PAD_GPIO_B1_11__ENET_enet_rx_er 0x01a8 0x0398 0x0440 3 1
+#define IMXRT_PAD_GPIO_B1_11__FLEXIO2_IO27 0x01a8 0x0398 0x0000 4 0
+#define IMXRT_PAD_GPIO_B1_11__GPIO2_gpio_io27 0x01a8 0x0398 0x0000 5 0
+#define IMXRT_PAD_GPIO_B1_11__LPSPI4_PCS3 0x01a8 0x0398 0x0000 6 0
+
+/* GPIO_B1_12 */
+#define IMXRT_PAD_GPIO_B1_12__LPUART5_TX 0x01ac 0x039c 0x054c 1 1
+#define IMXRT_PAD_GPIO_B1_12__CSI_csi_pixclk 0x01ac 0x039c 0x0424 2 1
+#define IMXRT_PAD_GPIO_B1_12__ENET_1588_EVENT0_IN 0x01ac 0x039c 0x0444 3 2
+#define IMXRT_PAD_GPIO_B1_12__FLEXIO2_IO28 0x01ac 0x039c 0x0000 4 0
+#define IMXRT_PAD_GPIO_B1_12__GPIO2_gpio_io28 0x01ac 0x039c 0x0000 5 0
+#define IMXRT_PAD_GPIO_B1_12__USDHC1_usdhc_cd_b 0x01ac 0x039c 0x05d4 6 2
+
+/* GPIO_B1_13 */
+#define IMXRT_PAD_GPIO_B1_13__WDOG1_wdog_b 0x01b0 0x03a0 0x0000 0 0
+#define IMXRT_PAD_GPIO_B1_13__LPUART5_RX 0x01b0 0x03a0 0x0548 1 1
+#define IMXRT_PAD_GPIO_B1_13__CSI_csi_vsync 0x01b0 0x03a0 0x0428 2 2
+#define IMXRT_PAD_GPIO_B1_13__ENET_1588_EVENT0_OUT 0x01b0 0x03a0 0x0000 3 0
+#define IMXRT_PAD_GPIO_B1_13__FLEXIO2_IO29 0x01b0 0x03a0 0x0000 4 0
+#define IMXRT_PAD_GPIO_B1_13__GPIO2_gpio_io29 0x01b0 0x03a0 0x0000 5 0
+#define IMXRT_PAD_GPIO_B1_13__USDHC1_usdhc_wp 0x01b0 0x03a0 0x05d8 6 3
+
+/* GPIO_B1_14 */
+#define IMXRT_PAD_GPIO_B1_14__ENET_enet_mdc 0x01b4 0x03a4 0x0000 0 0
+#define IMXRT_PAD_GPIO_B1_14__PWM4_A2 0x01b4 0x03a4 0x049c 1 1
+#define IMXRT_PAD_GPIO_B1_14__CSI_csi_hsync 0x01b4 0x03a4 0x0420 2 2
+#define IMXRT_PAD_GPIO_B1_14__XBARA1_IN02 0x01b4 0x03a4 0x060c 3 1
+#define IMXRT_PAD_GPIO_B1_14__FLEXIO2_IO30 0x01b4 0x03a4 0x0000 4 0
+#define IMXRT_PAD_GPIO_B1_14__GPIO2_gpio_io30 0x01b4 0x03a4 0x0000 5 0
+#define IMXRT_PAD_GPIO_B1_14__USDHC1_usdhc_vselect 0x01b4 0x03a4 0x0000 6 0
+
+/* GPIO_B1_15 */
+#define IMXRT_PAD_GPIO_B1_15__ENET_enet_mdio 0x01b8 0x03a8 0x0430 0 2
+#define IMXRT_PAD_GPIO_B1_15__PWM4_A3 0x01b8 0x03a8 0x04a0 1 1
+#define IMXRT_PAD_GPIO_B1_15__CSI_csi_mclk 0x01b8 0x03a8 0x0000 2 0
+#define IMXRT_PAD_GPIO_B1_15__XBARA1_IN03 0x01b8 0x03a8 0x0610 3 1
+#define IMXRT_PAD_GPIO_B1_15__FLEXIO2_IO31 0x01b8 0x03a8 0x0000 4 0
+#define IMXRT_PAD_GPIO_B1_15__GPIO2_gpio_io31 0x01b8 0x03a8 0x0000 5 0
+#define IMXRT_PAD_GPIO_B1_15__USDHC1_usdhc_reset_b 0x01b8 0x03a8 0x0000 6 0
+
+/* GPIO_EMC_00 */
+#define IMXRT_PAD_GPIO_EMC_00__SEMC_DATA00 0x0014 0x0204 0x0000 0 0
+#define IMXRT_PAD_GPIO_EMC_00__PWM4_A0 0x0014 0x0204 0x0494 1 0
+#define IMXRT_PAD_GPIO_EMC_00__LPSPI2_SCK 0x0014 0x0204 0x0500 2 1
+#define IMXRT_PAD_GPIO_EMC_00__XBARA1_IN02 0x0014 0x0204 0x060c 3 0
+#define IMXRT_PAD_GPIO_EMC_00__FLEXIO1_IO00 0x0014 0x0204 0x0000 4 0
+#define IMXRT_PAD_GPIO_EMC_00__GPIO4_gpio_io00 0x0014 0x0204 0x0000 5 0
+
+/* GPIO_EMC_01 */
+#define IMXRT_PAD_GPIO_EMC_01__SEMC_DATA01 0x0018 0x0208 0x0000 0 0
+#define IMXRT_PAD_GPIO_EMC_01__PWM4_B0 0x0018 0x0208 0x0000 1 0
+#define IMXRT_PAD_GPIO_EMC_01__LPSPI2_PCS0 0x0018 0x0208 0x04fc 2 1
+#define IMXRT_PAD_GPIO_EMC_01__XBARA1_IN03 0x0018 0x0208 0x0610 3 0
+#define IMXRT_PAD_GPIO_EMC_01__FLEXIO1_IO01 0x0018 0x0208 0x0000 4 0
+#define IMXRT_PAD_GPIO_EMC_01__GPIO4_gpio_io01 0x0018 0x0208 0x0000 5 0
+
+/* GPIO_EMC_02 */
+#define IMXRT_PAD_GPIO_EMC_02__SEMC_DATA02 0x001c 0x020c 0x0000 0 0
+#define IMXRT_PAD_GPIO_EMC_02__PWM4_A1 0x001c 0x020c 0x0498 1 0
+#define IMXRT_PAD_GPIO_EMC_02__LPSPI2_SDO 0x001c 0x020c 0x0508 2 1
+#define IMXRT_PAD_GPIO_EMC_02__XBARA1_OUT04 0x001c 0x020c 0x0614 3 0 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_4 to 0x1 */
+#define IMXRT_PAD_GPIO_EMC_02__XBARA1_IN04 0x001c 0x020c 0x0614 3 0 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_4 to 0 */
+#define IMXRT_PAD_GPIO_EMC_02__FLEXIO1_IO02 0x001c 0x020c 0x0000 4 0
+#define IMXRT_PAD_GPIO_EMC_02__GPIO4_gpio_io02 0x001c 0x020c 0x0000 5 0
+
+/* GPIO_EMC_03 */
+#define IMXRT_PAD_GPIO_EMC_03__SEMC_DATA03 0x0020 0x0210 0x0000 0 0
+#define IMXRT_PAD_GPIO_EMC_03__PWM4_B1 0x0020 0x0210 0x0000 1 0
+#define IMXRT_PAD_GPIO_EMC_03__LPSPI2_SDI 0x0020 0x0210 0x0504 2 1
+#define IMXRT_PAD_GPIO_EMC_03__XBARA1_OUT05 0x0020 0x0210 0x0618 3 0 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_5 to 0x1 */
+#define IMXRT_PAD_GPIO_EMC_03__XBARA1_IN05 0x0020 0x0210 0x0618 3 0 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_5 to 0 */
+#define IMXRT_PAD_GPIO_EMC_03__FLEXIO1_IO03 0x0020 0x0210 0x0000 4 0
+#define IMXRT_PAD_GPIO_EMC_03__GPIO4_gpio_io03 0x0020 0x0210 0x0000 5 0
+
+/* GPIO_EMC_04 */
+#define IMXRT_PAD_GPIO_EMC_04__SEMC_DATA04 0x0024 0x0214 0x0000 0 0
+#define IMXRT_PAD_GPIO_EMC_04__PWM4_A2 0x0024 0x0214 0x049c 1 0
+#define IMXRT_PAD_GPIO_EMC_04__SAI2_sai_tx_data 0x0024 0x0214 0x0000 2 0
+#define IMXRT_PAD_GPIO_EMC_04__XBARA1_OUT06 0x0024 0x0214 0x061c 3 0 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_6 to 0x1 */
+#define IMXRT_PAD_GPIO_EMC_04__XBARA1_IN06 0x0024 0x0214 0x061c 3 0 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_6 to 0 */
+#define IMXRT_PAD_GPIO_EMC_04__FLEXIO1_IO04 0x0024 0x0214 0x0000 4 0
+#define IMXRT_PAD_GPIO_EMC_04__GPIO4_gpio_io04 0x0024 0x0214 0x0000 5 0
+
+/* GPIO_EMC_05 */
+#define IMXRT_PAD_GPIO_EMC_05__SEMC_DATA05 0x0028 0x0218 0x0000 0 0
+#define IMXRT_PAD_GPIO_EMC_05__PWM4_B2 0x0028 0x0218 0x0000 1 0
+#define IMXRT_PAD_GPIO_EMC_05__SAI2_sai_tx_sync 0x0028 0x0218 0x05c4 2 0
+#define IMXRT_PAD_GPIO_EMC_05__XBARA1_OUT07 0x0028 0x0218 0x0620 3 0 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_7 to 0x1 */
+#define IMXRT_PAD_GPIO_EMC_05__XBARA1_IN07 0x0028 0x0218 0x0620 3 0 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_7 to 0 */
+#define IMXRT_PAD_GPIO_EMC_05__FLEXIO1_IO05 0x0028 0x0218 0x0000 4 0
+#define IMXRT_PAD_GPIO_EMC_05__GPIO4_gpio_io05 0x0028 0x0218 0x0000 5 0
+
+/* GPIO_EMC_06 */
+#define IMXRT_PAD_GPIO_EMC_06__SEMC_DATA06 0x002c 0x021c 0x0000 0 0
+#define IMXRT_PAD_GPIO_EMC_06__PWM2_A0 0x002c 0x021c 0x0478 1 0
+#define IMXRT_PAD_GPIO_EMC_06__SAI2_sai_tx_bclk 0x002c 0x021c 0x05c0 2 0
+#define IMXRT_PAD_GPIO_EMC_06__XBARA1_OUT08 0x002c 0x021c 0x0624 3 0 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_8 to 0x1 */
+#define IMXRT_PAD_GPIO_EMC_06__XBARA1_IN08 0x002c 0x021c 0x0624 3 0 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_8 to 0 */
+#define IMXRT_PAD_GPIO_EMC_06__FLEXIO1_IO06 0x002c 0x021c 0x0000 4 0
+#define IMXRT_PAD_GPIO_EMC_06__GPIO4_gpio_io06 0x002c 0x021c 0x0000 5 0
+
+/* GPIO_EMC_07 */
+#define IMXRT_PAD_GPIO_EMC_07__SEMC_DATA07 0x0030 0x0220 0x0000 0 0
+#define IMXRT_PAD_GPIO_EMC_07__PWM2_B0 0x0030 0x0220 0x0488 1 0
+#define IMXRT_PAD_GPIO_EMC_07__SAI2_sai_mclk 0x0030 0x0220 0x05b0 2 0
+#define IMXRT_PAD_GPIO_EMC_07__XBARA1_OUT09 0x0030 0x0220 0x0628 3 0 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_9 to 0x1 */
+#define IMXRT_PAD_GPIO_EMC_07__XBARA1_IN09 0x0030 0x0220 0x0628 3 0 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_9 to 0 */
+#define IMXRT_PAD_GPIO_EMC_07__FLEXIO1_IO07 0x0030 0x0220 0x0000 4 0
+#define IMXRT_PAD_GPIO_EMC_07__GPIO4_gpio_io07 0x0030 0x0220 0x0000 5 0
+
+/* GPIO_EMC_08 */
+#define IMXRT_PAD_GPIO_EMC_08__SEMC_DM0 0x0034 0x0224 0x0000 0 0
+#define IMXRT_PAD_GPIO_EMC_08__PWM2_A1 0x0034 0x0224 0x047c 1 0
+#define IMXRT_PAD_GPIO_EMC_08__SAI2_sai_rx_data 0x0034 0x0224 0x05b8 2 0
+#define IMXRT_PAD_GPIO_EMC_08__XBARA1_OUT17 0x0034 0x0224 0x062c 3 0 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_17 to 0x1 */
+#define IMXRT_PAD_GPIO_EMC_08__XBARA1_IN17 0x0034 0x0224 0x062c 3 0 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_17 to 0 */
+#define IMXRT_PAD_GPIO_EMC_08__FLEXIO1_IO08 0x0034 0x0224 0x0000 4 0
+#define IMXRT_PAD_GPIO_EMC_08__GPIO4_gpio_io08 0x0034 0x0224 0x0000 5 0
+
+/* GPIO_EMC_09 */
+#define IMXRT_PAD_GPIO_EMC_09__SEMC_ADDR00 0x0038 0x0228 0x0000 0 0
+#define IMXRT_PAD_GPIO_EMC_09__PWM2_B1 0x0038 0x0228 0x048c 1 0
+#define IMXRT_PAD_GPIO_EMC_09__SAI2_sai_rx_sync 0x0038 0x0228 0x05bc 2 0
+#define IMXRT_PAD_GPIO_EMC_09__CAN2_TX 0x0038 0x0228 0x0000 3 0
+#define IMXRT_PAD_GPIO_EMC_09__FLEXIO1_IO09 0x0038 0x0228 0x0000 4 0
+#define IMXRT_PAD_GPIO_EMC_09__GPIO4_gpio_io09 0x0038 0x0228 0x0000 5 0
+
+/* GPIO_EMC_10 */
+#define IMXRT_PAD_GPIO_EMC_10__SEMC_ADDR01 0x003c 0x022c 0x0000 0 0
+#define IMXRT_PAD_GPIO_EMC_10__PWM2_A2 0x003c 0x022c 0x0480 1 0
+#define IMXRT_PAD_GPIO_EMC_10__SAI2_sai_rx_bclk 0x003c 0x022c 0x05b4 2 0
+#define IMXRT_PAD_GPIO_EMC_10__CAN2_RX 0x003c 0x022c 0x0450 3 0
+#define IMXRT_PAD_GPIO_EMC_10__FLEXIO1_IO10 0x003c 0x022c 0x0000 4 0
+#define IMXRT_PAD_GPIO_EMC_10__GPIO4_gpio_io10 0x003c 0x022c 0x0000 5 0
+
+/* GPIO_EMC_11 */
+#define IMXRT_PAD_GPIO_EMC_11__SEMC_ADDR02 0x0040 0x0230 0x0000 0 0
+#define IMXRT_PAD_GPIO_EMC_11__PWM2_B2 0x0040 0x0230 0x0490 1 0
+#define IMXRT_PAD_GPIO_EMC_11__LPI2C4_SDA 0x0040 0x0230 0x04e8 2 0
+#define IMXRT_PAD_GPIO_EMC_11__USDHC2_usdhc_reset_b 0x0040 0x0230 0x0000 3 0
+#define IMXRT_PAD_GPIO_EMC_11__FLEXIO1_IO11 0x0040 0x0230 0x0000 4 0
+#define IMXRT_PAD_GPIO_EMC_11__GPIO4_gpio_io11 0x0040 0x0230 0x0000 5 0
+
+/* GPIO_EMC_12 */
+#define IMXRT_PAD_GPIO_EMC_12__SEMC_ADDR03 0x0044 0x0234 0x0000 0 0
+#define IMXRT_PAD_GPIO_EMC_12__XBARA1_IN24 0x0044 0x0234 0x0640 1 0
+#define IMXRT_PAD_GPIO_EMC_12__LPI2C4_SCL 0x0044 0x0234 0x04e4 2 0
+#define IMXRT_PAD_GPIO_EMC_12__USDHC1_usdhc_wp 0x0044 0x0234 0x05d8 3 0
+#define IMXRT_PAD_GPIO_EMC_12__PWM1_A3 0x0044 0x0234 0x0454 4 1
+#define IMXRT_PAD_GPIO_EMC_12__GPIO4_gpio_io12 0x0044 0x0234 0x0000 5 0
+
+/* GPIO_EMC_13 */
+#define IMXRT_PAD_GPIO_EMC_13__SEMC_ADDR04 0x0048 0x0238 0x0000 0 0
+#define IMXRT_PAD_GPIO_EMC_13__XBARA1_IN25 0x0048 0x0238 0x0650 1 1
+#define IMXRT_PAD_GPIO_EMC_13__LPUART3_TX 0x0048 0x0238 0x053c 2 1
+#define IMXRT_PAD_GPIO_EMC_13__MQS_RIGHT 0x0048 0x0238 0x0000 3 0
+#define IMXRT_PAD_GPIO_EMC_13__PWM1_B3 0x0048 0x0238 0x0464 4 1
+#define IMXRT_PAD_GPIO_EMC_13__GPIO4_gpio_io13 0x0048 0x0238 0x0000 5 0
+
+/* GPIO_EMC_14 */
+#define IMXRT_PAD_GPIO_EMC_14__SEMC_ADDR05 0x004c 0x023c 0x0000 0 0
+#define IMXRT_PAD_GPIO_EMC_14__XBARA1_OUT19 0x004c 0x023c 0x0654 1 0 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_19 to 0x1 */
+#define IMXRT_PAD_GPIO_EMC_14__XBARA1_IN19 0x004c 0x023c 0x0654 1 0 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_19 to 0 */
+#define IMXRT_PAD_GPIO_EMC_14__LPUART3_RX 0x004c 0x023c 0x0538 2 1
+#define IMXRT_PAD_GPIO_EMC_14__MQS_LEFT 0x004c 0x023c 0x0000 3 0
+#define IMXRT_PAD_GPIO_EMC_14__LPSPI2_PCS1 0x004c 0x023c 0x0000 4 0
+#define IMXRT_PAD_GPIO_EMC_14__GPIO4_gpio_io14 0x004c 0x023c 0x0000 5 0
+
+/* GPIO_EMC_15 */
+#define IMXRT_PAD_GPIO_EMC_15__SEMC_ADDR06 0x0050 0x0240 0x0000 0 0
+#define IMXRT_PAD_GPIO_EMC_15__XBARA1_IN20 0x0050 0x0240 0x0634 1 0
+#define IMXRT_PAD_GPIO_EMC_15__LPUART3_CTS_B 0x0050 0x0240 0x0534 2 0
+#define IMXRT_PAD_GPIO_EMC_15__SPDIF_spdif_out 0x0050 0x0240 0x0000 3 0
+#define IMXRT_PAD_GPIO_EMC_15__TMR3_TIMER0 0x0050 0x0240 0x057c 4 0 /* Maybe you want to set IOMUXC_GPR_GPR6 QTIMER3_TRM0_INPUT_SEL to 0 */
+#define IMXRT_PAD_GPIO_EMC_15__GPIO4_gpio_io15 0x0050 0x0240 0x0000 5 0
+
+/* GPIO_EMC_16 */
+#define IMXRT_PAD_GPIO_EMC_16__SEMC_ADDR07 0x0054 0x0244 0x0000 0 0
+#define IMXRT_PAD_GPIO_EMC_16__XBARA1_IN21 0x0054 0x0244 0x0658 1 0
+#define IMXRT_PAD_GPIO_EMC_16__LPUART3_RTS_B 0x0054 0x0244 0x0000 2 0
+#define IMXRT_PAD_GPIO_EMC_16__SPDIF_spdif_in 0x0054 0x0244 0x05c8 3 1
+#define IMXRT_PAD_GPIO_EMC_16__TMR3_TIMER1 0x0054 0x0244 0x0580 4 1 /* Maybe you want to set IOMUXC_GPR_GPR6 QTIMER3_TRM1_INPUT_SEL to 0 */
+#define IMXRT_PAD_GPIO_EMC_16__GPIO4_gpio_io16 0x0054 0x0244 0x0000 5 0
+
+/* GPIO_EMC_17 */
+#define IMXRT_PAD_GPIO_EMC_17__SEMC_ADDR08 0x0058 0x0248 0x0000 0 0
+#define IMXRT_PAD_GPIO_EMC_17__PWM4_A3 0x0058 0x0248 0x04a0 1 0
+#define IMXRT_PAD_GPIO_EMC_17__LPUART4_CTS_B 0x0058 0x0248 0x0000 2 0
+#define IMXRT_PAD_GPIO_EMC_17__CAN1_TX 0x0058 0x0248 0x0000 3 0
+#define IMXRT_PAD_GPIO_EMC_17__TMR3_TIMER2 0x0058 0x0248 0x0584 4 0 /* Maybe you want to set IOMUXC_GPR_GPR6 QTIMER3_TRM2_INPUT_SEL to 0 */
+#define IMXRT_PAD_GPIO_EMC_17__GPIO4_gpio_io17 0x0058 0x0248 0x0000 5 0
+
+/* GPIO_EMC_18 */
+#define IMXRT_PAD_GPIO_EMC_18__SEMC_ADDR09 0x005c 0x024c 0x0000 0 0
+#define IMXRT_PAD_GPIO_EMC_18__PWM4_B3 0x005c 0x024c 0x0000 1 0
+#define IMXRT_PAD_GPIO_EMC_18__LPUART4_RTS_B 0x005c 0x024c 0x0000 2 0
+#define IMXRT_PAD_GPIO_EMC_18__CAN1_RX 0x005c 0x024c 0x044c 3 1
+#define IMXRT_PAD_GPIO_EMC_18__TMR3_TIMER3 0x005c 0x024c 0x0588 4 0 /* Maybe you want to set IOMUXC_GPR_GPR6 QTIMER3_TRM3_INPUT_SEL to 0 */
+#define IMXRT_PAD_GPIO_EMC_18__GPIO4_gpio_io18 0x005c 0x024c 0x0000 5 0
+#define IMXRT_PAD_GPIO_EMC_18__SNVS_snvs_vio_5_ctl 0x005c 0x024c 0x0000 6 0
+
+/* GPIO_EMC_19 */
+#define IMXRT_PAD_GPIO_EMC_19__SEMC_ADDR11 0x0060 0x0250 0x0000 0 0
+#define IMXRT_PAD_GPIO_EMC_19__PWM2_A3 0x0060 0x0250 0x0474 1 1
+#define IMXRT_PAD_GPIO_EMC_19__LPUART4_TX 0x0060 0x0250 0x0544 2 1
+#define IMXRT_PAD_GPIO_EMC_19__ENET_enet_rx_data1 0x0060 0x0250 0x0438 3 0
+#define IMXRT_PAD_GPIO_EMC_19__TMR2_TIMER0 0x0060 0x0250 0x056c 4 0 /* Maybe you want to set IOMUXC_GPR_GPR6 QTIMER2_TRM0_INPUT_SEL to 0 */
+#define IMXRT_PAD_GPIO_EMC_19__GPIO4_gpio_io19 0x0060 0x0250 0x0000 5 0
+#define IMXRT_PAD_GPIO_EMC_19__SNVS_snvs_vio_5_b 0x0060 0x0250 0x0000 6 0
+
+/* GPIO_EMC_20 */
+#define IMXRT_PAD_GPIO_EMC_20__SEMC_ADDR12 0x0064 0x0254 0x0000 0 0
+#define IMXRT_PAD_GPIO_EMC_20__PWM2_B3 0x0064 0x0254 0x0484 1 1
+#define IMXRT_PAD_GPIO_EMC_20__LPUART4_RX 0x0064 0x0254 0x0540 2 1
+#define IMXRT_PAD_GPIO_EMC_20__ENET_enet_rx_data0 0x0064 0x0254 0x0434 3 0
+#define IMXRT_PAD_GPIO_EMC_20__TMR2_TIMER1 0x0064 0x0254 0x0570 4 0 /* Maybe you want to set IOMUXC_GPR_GPR6 QTIMER2_TRM1_INPUT_SEL to 0 */
+#define IMXRT_PAD_GPIO_EMC_20__GPIO4_gpio_io20 0x0064 0x0254 0x0000 5 0
+
+/* GPIO_EMC_21 */
+#define IMXRT_PAD_GPIO_EMC_21__SEMC_BA0 0x0068 0x0258 0x0000 0 0
+#define IMXRT_PAD_GPIO_EMC_21__PWM3_A3 0x0068 0x0258 0x0000 1 0
+#define IMXRT_PAD_GPIO_EMC_21__LPI2C3_SDA 0x0068 0x0258 0x04e0 2 0
+#define IMXRT_PAD_GPIO_EMC_21__ENET_enet_tx_data1 0x0068 0x0258 0x0000 3 0
+#define IMXRT_PAD_GPIO_EMC_21__TMR2_TIMER2 0x0068 0x0258 0x0574 4 0 /* Maybe you want to set IOMUXC_GPR_GPR6 QTIMER2_TRM2_INPUT_SEL to 0 */
+#define IMXRT_PAD_GPIO_EMC_21__GPIO4_gpio_io21 0x0068 0x0258 0x0000 5 0
+
+/* GPIO_EMC_22 */
+#define IMXRT_PAD_GPIO_EMC_22__SEMC_BA1 0x006c 0x025c 0x0000 0 0
+#define IMXRT_PAD_GPIO_EMC_22__PWM3_B3 0x006c 0x025c 0x0000 1 0
+#define IMXRT_PAD_GPIO_EMC_22__LPI2C3_SCL 0x006c 0x025c 0x04dc 2 0
+#define IMXRT_PAD_GPIO_EMC_22__ENET_enet_tx_data0 0x006c 0x025c 0x0000 3 0
+#define IMXRT_PAD_GPIO_EMC_22__TMR2_TIMER3 0x006c 0x025c 0x0578 4 0 /* Maybe you want to set IOMUXC_GPR_GPR6 QTIMER2_TRM3_INPUT_SEL to 0 */
+#define IMXRT_PAD_GPIO_EMC_22__GPIO4_gpio_io22 0x006c 0x025c 0x0000 5 0
+
+/* GPIO_EMC_23 */
+#define IMXRT_PAD_GPIO_EMC_23__SEMC_ADDR10 0x0070 0x0260 0x0000 0 0
+#define IMXRT_PAD_GPIO_EMC_23__PWM1_A0 0x0070 0x0260 0x0458 1 0
+#define IMXRT_PAD_GPIO_EMC_23__LPUART5_TX 0x0070 0x0260 0x054c 2 0
+#define IMXRT_PAD_GPIO_EMC_23__ENET_enet_rx_en 0x0070 0x0260 0x043c 3 0
+#define IMXRT_PAD_GPIO_EMC_23__GPT1_gpt_capture2 0x0070 0x0260 0x0000 4 0
+#define IMXRT_PAD_GPIO_EMC_23__GPIO4_gpio_io23 0x0070 0x0260 0x0000 5 0
+
+/* GPIO_EMC_24 */
+#define IMXRT_PAD_GPIO_EMC_24__SEMC_semc_cas 0x0074 0x0264 0x0000 0 0
+#define IMXRT_PAD_GPIO_EMC_24__PWM1_B0 0x0074 0x0264 0x0468 1 0
+#define IMXRT_PAD_GPIO_EMC_24__LPUART5_RX 0x0074 0x0264 0x0548 2 0
+#define IMXRT_PAD_GPIO_EMC_24__ENET_enet_tx_en 0x0074 0x0264 0x0000 3 0
+#define IMXRT_PAD_GPIO_EMC_24__GPT1_gpt_capture1 0x0074 0x0264 0x0000 4 0
+#define IMXRT_PAD_GPIO_EMC_24__GPIO4_gpio_io24 0x0074 0x0264 0x0000 5 0
+
+/* GPIO_EMC_25 */
+#define IMXRT_PAD_GPIO_EMC_25__SEMC_semc_ras 0x0078 0x0268 0x0000 0 0
+#define IMXRT_PAD_GPIO_EMC_25__PWM1_A1 0x0078 0x0268 0x045c 1 0
+#define IMXRT_PAD_GPIO_EMC_25__LPUART6_TX 0x0078 0x0268 0x0554 2 0
+#define IMXRT_PAD_GPIO_EMC_25__ENET_enet_tx_clk 0x0078 0x0268 0x0448 3 0
+#define IMXRT_PAD_GPIO_EMC_25__ENET_enet_ref_clk 0x0078 0x0268 0x042c 4 0
+#define IMXRT_PAD_GPIO_EMC_25__GPIO4_gpio_io25 0x0078 0x0268 0x0000 5 0
+
+/* GPIO_EMC_26 */
+#define IMXRT_PAD_GPIO_EMC_26__SEMC_semc_clk 0x007c 0x026c 0x0000 0 0
+#define IMXRT_PAD_GPIO_EMC_26__PWM1_B1 0x007c 0x026c 0x046c 1 0
+#define IMXRT_PAD_GPIO_EMC_26__LPUART6_RX 0x007c 0x026c 0x0550 2 0
+#define IMXRT_PAD_GPIO_EMC_26__ENET_enet_rx_er 0x007c 0x026c 0x0440 3 0
+#define IMXRT_PAD_GPIO_EMC_26__FLEXIO1_IO12 0x007c 0x026c 0x0000 4 0
+#define IMXRT_PAD_GPIO_EMC_26__GPIO4_gpio_io26 0x007c 0x026c 0x0000 5 0
+
+/* GPIO_EMC_27 */
+#define IMXRT_PAD_GPIO_EMC_27__SEMC_semc_cke 0x0080 0x0270 0x0000 0 0
+#define IMXRT_PAD_GPIO_EMC_27__PWM1_A2 0x0080 0x0270 0x0460 1 0
+#define IMXRT_PAD_GPIO_EMC_27__LPUART5_RTS_B 0x0080 0x0270 0x0000 2 0
+#define IMXRT_PAD_GPIO_EMC_27__LPSPI1_SCK 0x0080 0x0270 0x04f0 3 0
+#define IMXRT_PAD_GPIO_EMC_27__FLEXIO1_IO13 0x0080 0x0270 0x0000 4 0
+#define IMXRT_PAD_GPIO_EMC_27__GPIO4_gpio_io27 0x0080 0x0270 0x0000 5 0
+
+/* GPIO_EMC_28 */
+#define IMXRT_PAD_GPIO_EMC_28__SEMC_semc_we 0x0084 0x0274 0x0000 0 0
+#define IMXRT_PAD_GPIO_EMC_28__PWM1_B2 0x0084 0x0274 0x0470 1 0
+#define IMXRT_PAD_GPIO_EMC_28__LPUART5_CTS_B 0x0084 0x0274 0x0000 2 0
+#define IMXRT_PAD_GPIO_EMC_28__LPSPI1_SDO 0x0084 0x0274 0x04f8 3 0
+#define IMXRT_PAD_GPIO_EMC_28__FLEXIO1_IO14 0x0084 0x0274 0x0000 4 0
+#define IMXRT_PAD_GPIO_EMC_28__GPIO4_gpio_io28 0x0084 0x0274 0x0000 5 0
+
+/* GPIO_EMC_29 */
+#define IMXRT_PAD_GPIO_EMC_29__SEMC_CS0 0x0088 0x0278 0x0000 0 0
+#define IMXRT_PAD_GPIO_EMC_29__PWM3_A0 0x0088 0x0278 0x0000 1 0
+#define IMXRT_PAD_GPIO_EMC_29__LPUART6_RTS_B 0x0088 0x0278 0x0000 2 0
+#define IMXRT_PAD_GPIO_EMC_29__LPSPI1_SDI 0x0088 0x0278 0x04f4 3 0
+#define IMXRT_PAD_GPIO_EMC_29__FLEXIO1_IO15 0x0088 0x0278 0x0000 4 0
+#define IMXRT_PAD_GPIO_EMC_29__GPIO4_gpio_io29 0x0088 0x0278 0x0000 5 0
+
+/* GPIO_EMC_30 */
+#define IMXRT_PAD_GPIO_EMC_30__SEMC_DATA08 0x008c 0x027c 0x0000 0 0
+#define IMXRT_PAD_GPIO_EMC_30__PWM3_B0 0x008c 0x027c 0x0000 1 0
+#define IMXRT_PAD_GPIO_EMC_30__LPUART6_CTS_B 0x008c 0x027c 0x0000 2 0
+#define IMXRT_PAD_GPIO_EMC_30__LPSPI1_PCS0 0x008c 0x027c 0x04ec 3 1
+#define IMXRT_PAD_GPIO_EMC_30__CSI_csi_data23 0x008c 0x027c 0x0000 4 0
+#define IMXRT_PAD_GPIO_EMC_30__GPIO4_gpio_io30 0x008c 0x027c 0x0000 5 0
+
+/* GPIO_EMC_31 */
+#define IMXRT_PAD_GPIO_EMC_31__SEMC_DATA09 0x0090 0x0280 0x0000 0 0
+#define IMXRT_PAD_GPIO_EMC_31__PWM3_A1 0x0090 0x0280 0x0000 1 0
+#define IMXRT_PAD_GPIO_EMC_31__LPUART7_TX 0x0090 0x0280 0x055c 2 1
+#define IMXRT_PAD_GPIO_EMC_31__LPSPI1_PCS1 0x0090 0x0280 0x0000 3 0
+#define IMXRT_PAD_GPIO_EMC_31__CSI_csi_data22 0x0090 0x0280 0x0000 4 0
+#define IMXRT_PAD_GPIO_EMC_31__GPIO4_gpio_io31 0x0090 0x0280 0x0000 5 0
+
+/* GPIO_EMC_32 */
+#define IMXRT_PAD_GPIO_EMC_32__SEMC_DATA10 0x0094 0x0284 0x0000 0 0
+#define IMXRT_PAD_GPIO_EMC_32__PWM3_B1 0x0094 0x0284 0x0000 1 0
+#define IMXRT_PAD_GPIO_EMC_32__LPUART7_RX 0x0094 0x0284 0x0558 2 1
+#define IMXRT_PAD_GPIO_EMC_32__CCM_PMIC_RDY 0x0094 0x0284 0x03fc 3 4
+#define IMXRT_PAD_GPIO_EMC_32__CSI_csi_data21 0x0094 0x0284 0x0000 4 0
+#define IMXRT_PAD_GPIO_EMC_32__GPIO3_gpio_io18 0x0094 0x0284 0x0000 5 0
+
+/* GPIO_EMC_33 */
+#define IMXRT_PAD_GPIO_EMC_33__SEMC_DATA11 0x0098 0x0288 0x0000 0 0
+#define IMXRT_PAD_GPIO_EMC_33__PWM3_A2 0x0098 0x0288 0x0000 1 0
+#define IMXRT_PAD_GPIO_EMC_33__USDHC1_usdhc_reset_b 0x0098 0x0288 0x0000 2 0
+#define IMXRT_PAD_GPIO_EMC_33__SAI3_sai_rx_data 0x0098 0x0288 0x0000 3 0
+#define IMXRT_PAD_GPIO_EMC_33__CSI_csi_data20 0x0098 0x0288 0x0000 4 0
+#define IMXRT_PAD_GPIO_EMC_33__GPIO3_gpio_io19 0x0098 0x0288 0x0000 5 0
+
+/* GPIO_EMC_34 */
+#define IMXRT_PAD_GPIO_EMC_34__SEMC_DATA12 0x009c 0x028c 0x0000 0 0
+#define IMXRT_PAD_GPIO_EMC_34__PWM3_B2 0x009c 0x028c 0x0000 1 0
+#define IMXRT_PAD_GPIO_EMC_34__USDHC1_usdhc_vselect 0x009c 0x028c 0x0000 2 0
+#define IMXRT_PAD_GPIO_EMC_34__SAI3_sai_rx_sync 0x009c 0x028c 0x0000 3 0
+#define IMXRT_PAD_GPIO_EMC_34__CSI_csi_data19 0x009c 0x028c 0x0000 4 0
+#define IMXRT_PAD_GPIO_EMC_34__GPIO3_gpio_io20 0x009c 0x028c 0x0000 5 0
+
+/* GPIO_EMC_35 */
+#define IMXRT_PAD_GPIO_EMC_35__SEMC_DATA13 0x00a0 0x0290 0x0000 0 0
+#define IMXRT_PAD_GPIO_EMC_35__XBARA1_OUT18 0x00a0 0x0290 0x0630 1 0 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_18 to 0x1 */
+#define IMXRT_PAD_GPIO_EMC_35__XBARA1_IN18 0x00a0 0x0290 0x0630 1 0 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_18 to 0 */
+#define IMXRT_PAD_GPIO_EMC_35__GPT1_gpt_compare1 0x00a0 0x0290 0x0000 2 0
+#define IMXRT_PAD_GPIO_EMC_35__SAI3_sai_rx_bclk 0x00a0 0x0290 0x0000 3 0
+#define IMXRT_PAD_GPIO_EMC_35__CSI_csi_data18 0x00a0 0x0290 0x0000 4 0
+#define IMXRT_PAD_GPIO_EMC_35__GPIO3_gpio_io21 0x00a0 0x0290 0x0000 5 0
+#define IMXRT_PAD_GPIO_EMC_35__USDHC1_usdhc_cd_b 0x00a0 0x0290 0x05d4 6 0
+
+/* GPIO_EMC_36 */
+#define IMXRT_PAD_GPIO_EMC_36__SEMC_DATA14 0x00a4 0x0294 0x0000 0 0
+#define IMXRT_PAD_GPIO_EMC_36__XBARA1_IN22 0x00a4 0x0294 0x0638 1 0
+#define IMXRT_PAD_GPIO_EMC_36__GPT1_gpt_compare2 0x00a4 0x0294 0x0000 2 0
+#define IMXRT_PAD_GPIO_EMC_36__SAI3_sai_tx_data 0x00a4 0x0294 0x0000 3 0
+#define IMXRT_PAD_GPIO_EMC_36__CSI_csi_data17 0x00a4 0x0294 0x0000 4 0
+#define IMXRT_PAD_GPIO_EMC_36__GPIO3_gpio_io22 0x00a4 0x0294 0x0000 5 0
+#define IMXRT_PAD_GPIO_EMC_36__USDHC1_usdhc_wp 0x00a4 0x0294 0x05d8 6 1
+
+/* GPIO_EMC_37 */
+#define IMXRT_PAD_GPIO_EMC_37__SEMC_DATA15 0x00a8 0x0298 0x0000 0 0
+#define IMXRT_PAD_GPIO_EMC_37__XBARA1_IN23 0x00a8 0x0298 0x063c 1 0
+#define IMXRT_PAD_GPIO_EMC_37__GPT1_gpt_compare3 0x00a8 0x0298 0x0000 2 0
+#define IMXRT_PAD_GPIO_EMC_37__SAI3_sai_mclk 0x00a8 0x0298 0x0000 3 0
+#define IMXRT_PAD_GPIO_EMC_37__CSI_csi_data16 0x00a8 0x0298 0x0000 4 0
+#define IMXRT_PAD_GPIO_EMC_37__GPIO3_gpio_io23 0x00a8 0x0298 0x0000 5 0
+#define IMXRT_PAD_GPIO_EMC_37__USDHC2_usdhc_wp 0x00a8 0x0298 0x0608 6 0
+
+/* GPIO_EMC_38 */
+#define IMXRT_PAD_GPIO_EMC_38__SEMC_DM1 0x00ac 0x029c 0x0000 0 0
+#define IMXRT_PAD_GPIO_EMC_38__PWM1_A3 0x00ac 0x029c 0x0454 1 2
+#define IMXRT_PAD_GPIO_EMC_38__LPUART8_TX 0x00ac 0x029c 0x0564 2 2
+#define IMXRT_PAD_GPIO_EMC_38__SAI3_sai_tx_bclk 0x00ac 0x029c 0x0000 3 0
+#define IMXRT_PAD_GPIO_EMC_38__CSI_csi_field 0x00ac 0x029c 0x0000 4 0
+#define IMXRT_PAD_GPIO_EMC_38__GPIO3_gpio_io24 0x00ac 0x029c 0x0000 5 0
+#define IMXRT_PAD_GPIO_EMC_38__USDHC2_usdhc_vselect 0x00ac 0x029c 0x0000 6 0
+
+/* GPIO_EMC_39 */
+#define IMXRT_PAD_GPIO_EMC_39__SEMC_semc_dqs 0x00b0 0x02a0 0x0000 0 0
+#define IMXRT_PAD_GPIO_EMC_39__PWM1_B3 0x00b0 0x02a0 0x0464 1 2
+#define IMXRT_PAD_GPIO_EMC_39__LPUART8_RX 0x00b0 0x02a0 0x0560 2 2
+#define IMXRT_PAD_GPIO_EMC_39__SAI3_sai_tx_sync 0x00b0 0x02a0 0x0000 3 0
+#define IMXRT_PAD_GPIO_EMC_39__WDOG1_wdog_b 0x00b0 0x02a0 0x0000 4 0
+#define IMXRT_PAD_GPIO_EMC_39__GPIO3_gpio_io25 0x00b0 0x02a0 0x0000 5 0
+#define IMXRT_PAD_GPIO_EMC_39__USDHC2_usdhc_cd_b 0x00b0 0x02a0 0x05e0 6 1
+
+/* GPIO_EMC_40 */
+#define IMXRT_PAD_GPIO_EMC_40__SEMC_semc_rdy 0x00b4 0x02a4 0x0000 0 0
+#define IMXRT_PAD_GPIO_EMC_40__GPT2_gpt_capture2 0x00b4 0x02a4 0x0000 1 0
+#define IMXRT_PAD_GPIO_EMC_40__LPSPI1_PCS2 0x00b4 0x02a4 0x0000 2 0
+#define IMXRT_PAD_GPIO_EMC_40__USB2_usb_otg2_oc 0x00b4 0x02a4 0x05cc 3 1
+#define IMXRT_PAD_GPIO_EMC_40__ENET_enet_mdc 0x00b4 0x02a4 0x0000 4 0
+#define IMXRT_PAD_GPIO_EMC_40__GPIO3_gpio_io26 0x00b4 0x02a4 0x0000 5 0
+#define IMXRT_PAD_GPIO_EMC_40__USDHC2_usdhc_reset_b 0x00b4 0x02a4 0x0000 6 0
+
+/* GPIO_EMC_41 */
+#define IMXRT_PAD_GPIO_EMC_41__SEMC_CSX0 0x00b8 0x02a8 0x0000 0 0
+#define IMXRT_PAD_GPIO_EMC_41__GPT2_gpt_capture1 0x00b8 0x02a8 0x0000 1 0
+#define IMXRT_PAD_GPIO_EMC_41__LPSPI1_PCS3 0x00b8 0x02a8 0x0000 2 0
+#define IMXRT_PAD_GPIO_EMC_41__USB2_usb_otg2_pwr 0x00b8 0x02a8 0x0000 3 0
+#define IMXRT_PAD_GPIO_EMC_41__ENET_enet_mdio 0x00b8 0x02a8 0x0430 4 1
+#define IMXRT_PAD_GPIO_EMC_41__GPIO3_gpio_io27 0x00b8 0x02a8 0x0000 5 0
+#define IMXRT_PAD_GPIO_EMC_41__USDHC1_usdhc_vselect 0x00b8 0x02a8 0x0000 6 0
+
+/* GPIO_SD_B0_00 */
+#define IMXRT_PAD_GPIO_SD_B0_00__USDHC1_usdhc_cmd 0x01bc 0x03ac 0x0000 0 0
+#define IMXRT_PAD_GPIO_SD_B0_00__PWM1_A0 0x01bc 0x03ac 0x0458 1 1
+#define IMXRT_PAD_GPIO_SD_B0_00__LPI2C3_SCL 0x01bc 0x03ac 0x04dc 2 1
+#define IMXRT_PAD_GPIO_SD_B0_00__XBARA1_OUT04 0x01bc 0x03ac 0x0614 3 1 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_4 to 0x1 */
+#define IMXRT_PAD_GPIO_SD_B0_00__XBARA1_IN04 0x01bc 0x03ac 0x0614 3 1 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_4 to 0 */
+#define IMXRT_PAD_GPIO_SD_B0_00__LPSPI1_SCK 0x01bc 0x03ac 0x04f0 4 1
+#define IMXRT_PAD_GPIO_SD_B0_00__GPIO3_gpio_io12 0x01bc 0x03ac 0x0000 5 0
+#define IMXRT_PAD_GPIO_SD_B0_00__FLEXSPI_FLEXSPI_A_SS1_B 0x01bc 0x03ac 0x0000 6 0
+
+/* GPIO_SD_B0_01 */
+#define IMXRT_PAD_GPIO_SD_B0_01__USDHC1_usdhc_clk 0x01c0 0x03b0 0x0000 0 0
+#define IMXRT_PAD_GPIO_SD_B0_01__PWM1_B0 0x01c0 0x03b0 0x0468 1 1
+#define IMXRT_PAD_GPIO_SD_B0_01__LPI2C3_SDA 0x01c0 0x03b0 0x04e0 2 1
+#define IMXRT_PAD_GPIO_SD_B0_01__XBARA1_OUT05 0x01c0 0x03b0 0x0618 3 1 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_5 to 0x1 */
+#define IMXRT_PAD_GPIO_SD_B0_01__XBARA1_IN05 0x01c0 0x03b0 0x0618 3 1 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_5 to 0 */
+#define IMXRT_PAD_GPIO_SD_B0_01__LPSPI1_PCS0 0x01c0 0x03b0 0x04ec 4 0
+#define IMXRT_PAD_GPIO_SD_B0_01__GPIO3_gpio_io13 0x01c0 0x03b0 0x0000 5 0
+#define IMXRT_PAD_GPIO_SD_B0_01__FLEXSPI_FLEXSPI_B_SS1_B 0x01c0 0x03b0 0x0000 6 0
+
+/* GPIO_SD_B0_02 */
+#define IMXRT_PAD_GPIO_SD_B0_02__USDHC1_usdhc_data0 0x01c4 0x03b4 0x0000 0 0
+#define IMXRT_PAD_GPIO_SD_B0_02__PWM1_A1 0x01c4 0x03b4 0x045c 1 1
+#define IMXRT_PAD_GPIO_SD_B0_02__LPUART8_CTS_B 0x01c4 0x03b4 0x0000 2 0
+#define IMXRT_PAD_GPIO_SD_B0_02__XBARA1_OUT06 0x01c4 0x03b4 0x061c 3 1 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_6 to 0x1 */
+#define IMXRT_PAD_GPIO_SD_B0_02__XBARA1_IN06 0x01c4 0x03b4 0x061c 3 1 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_6 to 0 */
+#define IMXRT_PAD_GPIO_SD_B0_02__LPSPI1_SDO 0x01c4 0x03b4 0x04f8 4 1
+#define IMXRT_PAD_GPIO_SD_B0_02__GPIO3_gpio_io14 0x01c4 0x03b4 0x0000 5 0
+
+/* GPIO_SD_B0_03 */
+#define IMXRT_PAD_GPIO_SD_B0_03__USDHC1_usdhc_data1 0x01c8 0x03b8 0x0000 0 0
+#define IMXRT_PAD_GPIO_SD_B0_03__PWM1_B1 0x01c8 0x03b8 0x046c 1 1
+#define IMXRT_PAD_GPIO_SD_B0_03__LPUART8_RTS_B 0x01c8 0x03b8 0x0000 2 0
+#define IMXRT_PAD_GPIO_SD_B0_03__XBARA1_OUT07 0x01c8 0x03b8 0x0620 3 1 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_7 to 0x1 */
+#define IMXRT_PAD_GPIO_SD_B0_03__XBARA1_IN07 0x01c8 0x03b8 0x0620 3 1 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_7 to 0 */
+#define IMXRT_PAD_GPIO_SD_B0_03__LPSPI1_SDI 0x01c8 0x03b8 0x04f4 4 1
+#define IMXRT_PAD_GPIO_SD_B0_03__GPIO3_gpio_io15 0x01c8 0x03b8 0x0000 5 0
+
+/* GPIO_SD_B0_04 */
+#define IMXRT_PAD_GPIO_SD_B0_04__USDHC1_usdhc_data2 0x01cc 0x03bc 0x0000 0 0
+#define IMXRT_PAD_GPIO_SD_B0_04__PWM1_A2 0x01cc 0x03bc 0x0460 1 1
+#define IMXRT_PAD_GPIO_SD_B0_04__LPUART8_TX 0x01cc 0x03bc 0x0564 2 0
+#define IMXRT_PAD_GPIO_SD_B0_04__XBARA1_OUT08 0x01cc 0x03bc 0x0624 3 1 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_8 to 0x1 */
+#define IMXRT_PAD_GPIO_SD_B0_04__XBARA1_IN08 0x01cc 0x03bc 0x0624 3 1 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_8 to 0 */
+#define IMXRT_PAD_GPIO_SD_B0_04__FLEXSPI_FLEXSPI_B_SS0_B 0x01cc 0x03bc 0x0000 4 0
+#define IMXRT_PAD_GPIO_SD_B0_04__GPIO3_gpio_io16 0x01cc 0x03bc 0x0000 5 0
+#define IMXRT_PAD_GPIO_SD_B0_04__CCM_CLKO1 0x01cc 0x03bc 0x0000 6 0
+
+/* GPIO_SD_B0_05 */
+#define IMXRT_PAD_GPIO_SD_B0_05__USDHC1_usdhc_data3 0x01d0 0x03c0 0x0000 0 0
+#define IMXRT_PAD_GPIO_SD_B0_05__PWM1_B2 0x01d0 0x03c0 0x0470 1 1
+#define IMXRT_PAD_GPIO_SD_B0_05__LPUART8_RX 0x01d0 0x03c0 0x0560 2 0
+#define IMXRT_PAD_GPIO_SD_B0_05__XBARA1_OUT09 0x01d0 0x03c0 0x0628 3 1 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_9 to 0x1 */
+#define IMXRT_PAD_GPIO_SD_B0_05__XBARA1_IN09 0x01d0 0x03c0 0x0628 3 1 /* Maybe you want to set IOMUXC_GPR_GPR6 IOMUXC_XBAR_DIR_SEL_9 to 0 */
+#define IMXRT_PAD_GPIO_SD_B0_05__FLEXSPI_FLEXSPI_B_DQS 0x01d0 0x03c0 0x0000 4 0
+#define IMXRT_PAD_GPIO_SD_B0_05__GPIO3_gpio_io17 0x01d0 0x03c0 0x0000 5 0
+#define IMXRT_PAD_GPIO_SD_B0_05__CCM_CLKO2 0x01d0 0x03c0 0x0000 6 0
+
+/* GPIO_SD_B1_00 */
+#define IMXRT_PAD_GPIO_SD_B1_00__USDHC2_usdhc_data3 0x01d4 0x03c4 0x05f4 0 0
+#define IMXRT_PAD_GPIO_SD_B1_00__FLEXSPI_FLEXSPI_B_DATA3 0x01d4 0x03c4 0x04c4 1 0
+#define IMXRT_PAD_GPIO_SD_B1_00__PWM1_A3 0x01d4 0x03c4 0x0454 2 0
+#define IMXRT_PAD_GPIO_SD_B1_00__SAI1_sai_tx_data3 0x01d4 0x03c4 0x0598 3 0
+#define IMXRT_PAD_GPIO_SD_B1_00__LPUART4_TX 0x01d4 0x03c4 0x0544 4 0
+#define IMXRT_PAD_GPIO_SD_B1_00__GPIO3_gpio_io00 0x01d4 0x03c4 0x0000 5 0
+
+/* GPIO_SD_B1_01 */
+#define IMXRT_PAD_GPIO_SD_B1_01__USDHC2_usdhc_data2 0x01d8 0x03c8 0x05f0 0 0
+#define IMXRT_PAD_GPIO_SD_B1_01__FLEXSPI_FLEXSPI_B_DATA2 0x01d8 0x03c8 0x04c0 1 0
+#define IMXRT_PAD_GPIO_SD_B1_01__PWM1_B3 0x01d8 0x03c8 0x0464 2 0
+#define IMXRT_PAD_GPIO_SD_B1_01__SAI1_sai_tx_data2 0x01d8 0x03c8 0x059c 3 0
+#define IMXRT_PAD_GPIO_SD_B1_01__LPUART4_RX 0x01d8 0x03c8 0x0540 4 0
+#define IMXRT_PAD_GPIO_SD_B1_01__GPIO3_gpio_io01 0x01d8 0x03c8 0x0000 5 0
+
+/* GPIO_SD_B1_02 */
+#define IMXRT_PAD_GPIO_SD_B1_02__USDHC2_usdhc_data1 0x01dc 0x03cc 0x05ec 0 0
+#define IMXRT_PAD_GPIO_SD_B1_02__FLEXSPI_FLEXSPI_B_DATA1 0x01dc 0x03cc 0x04bc 1 0
+#define IMXRT_PAD_GPIO_SD_B1_02__PWM2_A3 0x01dc 0x03cc 0x0474 2 0
+#define IMXRT_PAD_GPIO_SD_B1_02__SAI1_sai_tx_data1 0x01dc 0x03cc 0x05a0 3 0
+#define IMXRT_PAD_GPIO_SD_B1_02__CAN1_TX 0x01dc 0x03cc 0x0000 4 0
+#define IMXRT_PAD_GPIO_SD_B1_02__GPIO3_gpio_io02 0x01dc 0x03cc 0x0000 5 0
+#define IMXRT_PAD_GPIO_SD_B1_02__CCM_WAIT 0x01dc 0x03cc 0x0000 6 0
+
+/* GPIO_SD_B1_03 */
+#define IMXRT_PAD_GPIO_SD_B1_03__USDHC2_usdhc_data0 0x01e0 0x03d0 0x05e8 0 0
+#define IMXRT_PAD_GPIO_SD_B1_03__FLEXSPI_FLEXSPI_B_DATA0 0x01e0 0x03d0 0x04b8 1 0
+#define IMXRT_PAD_GPIO_SD_B1_03__PWM2_B3 0x01e0 0x03d0 0x0484 2 0
+#define IMXRT_PAD_GPIO_SD_B1_03__SAI1_sai_mclk 0x01e0 0x03d0 0x058c 3 0
+#define IMXRT_PAD_GPIO_SD_B1_03__CAN1_RX 0x01e0 0x03d0 0x044c 4 0
+#define IMXRT_PAD_GPIO_SD_B1_03__GPIO3_gpio_io03 0x01e0 0x03d0 0x0000 5 0
+#define IMXRT_PAD_GPIO_SD_B1_03__CCM_PMIC_RDY 0x01e0 0x03d0 0x03fc 6 0
+
+/* GPIO_SD_B1_04 */
+#define IMXRT_PAD_GPIO_SD_B1_04__USDHC2_usdhc_clk 0x01e4 0x03d4 0x05dc 0 0
+#define IMXRT_PAD_GPIO_SD_B1_04__FLEXSPI_FLEXSPI_B_SCLK 0x01e4 0x03d4 0x0000 1 0
+#define IMXRT_PAD_GPIO_SD_B1_04__LPI2C1_SCL 0x01e4 0x03d4 0x04cc 2 0
+#define IMXRT_PAD_GPIO_SD_B1_04__SAI1_sai_rx_sync 0x01e4 0x03d4 0x05a4 3 0
+#define IMXRT_PAD_GPIO_SD_B1_04__FLEXSPI_FLEXSPI_A_SS1_B 0x01e4 0x03d4 0x0000 4 0
+#define IMXRT_PAD_GPIO_SD_B1_04__GPIO3_gpio_io04 0x01e4 0x03d4 0x0000 5 0
+#define IMXRT_PAD_GPIO_SD_B1_04__CCM_STOP 0x01e4 0x03d4 0x0000 6 0
+
+/* GPIO_SD_B1_05 */
+#define IMXRT_PAD_GPIO_SD_B1_05__USDHC2_usdhc_cmd 0x01e8 0x03d8 0x05e4 0 0
+#define IMXRT_PAD_GPIO_SD_B1_05__FLEXSPI_FLEXSPI_A_DQS 0x01e8 0x03d8 0x04a4 1 0
+#define IMXRT_PAD_GPIO_SD_B1_05__LPI2C1_SDA 0x01e8 0x03d8 0x04d0 2 0
+#define IMXRT_PAD_GPIO_SD_B1_05__SAI1_sai_rx_bclk 0x01e8 0x03d8 0x0590 3 0
+#define IMXRT_PAD_GPIO_SD_B1_05__FLEXSPI_FLEXSPI_B_SS0_B 0x01e8 0x03d8 0x0000 4 0
+#define IMXRT_PAD_GPIO_SD_B1_05__GPIO3_gpio_io05 0x01e8 0x03d8 0x0000 5 0
+
+/* GPIO_SD_B1_06 */
+#define IMXRT_PAD_GPIO_SD_B1_06__USDHC2_usdhc_reset_b 0x01ec 0x03dc 0x0000 0 0
+#define IMXRT_PAD_GPIO_SD_B1_06__FLEXSPI_FLEXSPI_A_SS0_B 0x01ec 0x03dc 0x0000 1 0
+#define IMXRT_PAD_GPIO_SD_B1_06__LPUART7_CTS_B 0x01ec 0x03dc 0x0000 2 0
+#define IMXRT_PAD_GPIO_SD_B1_06__SAI1_sai_rx_data0 0x01ec 0x03dc 0x0594 3 0
+#define IMXRT_PAD_GPIO_SD_B1_06__LPSPI2_PCS0 0x01ec 0x03dc 0x04fc 4 0
+#define IMXRT_PAD_GPIO_SD_B1_06__GPIO3_gpio_io06 0x01ec 0x03dc 0x0000 5 0
+
+/* GPIO_SD_B1_07 */
+#define IMXRT_PAD_GPIO_SD_B1_07__SEMC_CSX1 0x01f0 0x03e0 0x0000 0 0
+#define IMXRT_PAD_GPIO_SD_B1_07__FLEXSPI_FLEXSPI_A_SCLK 0x01f0 0x03e0 0x04c8 1 0
+#define IMXRT_PAD_GPIO_SD_B1_07__LPUART7_RTS_B 0x01f0 0x03e0 0x0000 2 0
+#define IMXRT_PAD_GPIO_SD_B1_07__SAI1_sai_tx_data0 0x01f0 0x03e0 0x0000 3 0
+#define IMXRT_PAD_GPIO_SD_B1_07__LPSPI2_SCK 0x01f0 0x03e0 0x0500 4 0
+#define IMXRT_PAD_GPIO_SD_B1_07__GPIO3_gpio_io07 0x01f0 0x03e0 0x0000 5 0
+
+/* GPIO_SD_B1_08 */
+#define IMXRT_PAD_GPIO_SD_B1_08__USDHC2_usdhc_data4 0x01f4 0x03e4 0x05f8 0 0
+#define IMXRT_PAD_GPIO_SD_B1_08__FLEXSPI_FLEXSPI_A_DATA0 0x01f4 0x03e4 0x04a8 1 0
+#define IMXRT_PAD_GPIO_SD_B1_08__LPUART7_TX 0x01f4 0x03e4 0x055c 2 0
+#define IMXRT_PAD_GPIO_SD_B1_08__SAI1_sai_tx_bclk 0x01f4 0x03e4 0x05a8 3 0
+#define IMXRT_PAD_GPIO_SD_B1_08__LPSPI2_SDO 0x01f4 0x03e4 0x0508 4 0
+#define IMXRT_PAD_GPIO_SD_B1_08__GPIO3_gpio_io08 0x01f4 0x03e4 0x0000 5 0
+#define IMXRT_PAD_GPIO_SD_B1_08__SEMC_CSX2 0x01f4 0x03e4 0x0000 6 0
+
+/* GPIO_SD_B1_09 */
+#define IMXRT_PAD_GPIO_SD_B1_09__USDHC2_usdhc_data5 0x01f8 0x03e8 0x05fc 0 0
+#define IMXRT_PAD_GPIO_SD_B1_09__FLEXSPI_FLEXSPI_A_DATA1 0x01f8 0x03e8 0x04ac 1 0
+#define IMXRT_PAD_GPIO_SD_B1_09__LPUART7_RX 0x01f8 0x03e8 0x0558 2 0
+#define IMXRT_PAD_GPIO_SD_B1_09__SAI1_sai_tx_sync 0x01f8 0x03e8 0x05ac 3 0
+#define IMXRT_PAD_GPIO_SD_B1_09__LPSPI2_SDI 0x01f8 0x03e8 0x0504 4 0
+#define IMXRT_PAD_GPIO_SD_B1_09__GPIO3_gpio_io09 0x01f8 0x03e8 0x0000 5 0
+
+/* GPIO_SD_B1_10 */
+#define IMXRT_PAD_GPIO_SD_B1_10__USDHC2_usdhc_data6 0x01fc 0x03ec 0x0600 0 0
+#define IMXRT_PAD_GPIO_SD_B1_10__FLEXSPI_FLEXSPI_A_DATA2 0x01fc 0x03ec 0x04b0 1 0
+#define IMXRT_PAD_GPIO_SD_B1_10__LPUART2_RX 0x01fc 0x03ec 0x052c 2 0
+#define IMXRT_PAD_GPIO_SD_B1_10__LPI2C2_SDA 0x01fc 0x03ec 0x04d8 3 0
+#define IMXRT_PAD_GPIO_SD_B1_10__LPSPI2_PCS2 0x01fc 0x03ec 0x0000 4 0
+#define IMXRT_PAD_GPIO_SD_B1_10__GPIO3_gpio_io10 0x01fc 0x03ec 0x0000 5 0
+
+/* GPIO_SD_B1_11 */
+#define IMXRT_PAD_GPIO_SD_B1_11__USDHC2_usdhc_data7 0x0200 0x03f0 0x0604 0 0
+#define IMXRT_PAD_GPIO_SD_B1_11__FLEXSPI_FLEXSPI_A_DATA3 0x0200 0x03f0 0x04b4 1 0
+#define IMXRT_PAD_GPIO_SD_B1_11__LPUART2_TX 0x0200 0x03f0 0x0530 2 0
+#define IMXRT_PAD_GPIO_SD_B1_11__LPI2C2_SCL 0x0200 0x03f0 0x04d4 3 0
+#define IMXRT_PAD_GPIO_SD_B1_11__LPSPI2_PCS3 0x0200 0x03f0 0x0000 4 0
+#define IMXRT_PAD_GPIO_SD_B1_11__GPIO3_gpio_io11 0x0200 0x03f0 0x0000 5 0
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_IMXRT_IMXRT1050_PINFUNC_H */
diff --git a/bsps/arm/imxrt/include/imxrt/memory.h b/bsps/arm/imxrt/include/imxrt/memory.h
new file mode 100644
index 0000000000..5a6b457aa6
--- /dev/null
+++ b/bsps/arm/imxrt/include/imxrt/memory.h
@@ -0,0 +1,83 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SMEMORYL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_ARM_IMXRT_IMXRT_MEMORY_H
+#define LIBBSP_ARM_IMXRT_IMXRT_MEMORY_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern char imxrt_memory_null_begin[];
+extern char imxrt_memory_null_end[];
+extern char imxrt_memory_null_size[];
+
+extern char imxrt_memory_itcm_begin[];
+extern char imxrt_memory_itcm_end[];
+extern char imxrt_memory_itcm_size[];
+
+extern char imxrt_memory_dtcm_begin[];
+extern char imxrt_memory_dtcm_end[];
+extern char imxrt_memory_dtcm_size[];
+
+extern char imxrt_memory_ocram_begin[];
+extern char imxrt_memory_ocram_end[];
+extern char imxrt_memory_ocram_size[];
+
+extern char imxrt_memory_peripheral_begin[];
+extern char imxrt_memory_peripheral_end[];
+extern char imxrt_memory_peripheral_size[];
+
+extern char imxrt_memory_flexspi_config_begin[];
+extern char imxrt_memory_flexspi_config_end[];
+extern char imxrt_memory_flexspi_config_size[];
+
+extern char imxrt_memory_flexspi_ivt_begin[];
+extern char imxrt_memory_flexspi_ivt_end[];
+extern char imxrt_memory_flexspi_ivt_size[];
+
+extern char imxrt_memory_flexspi_begin[];
+extern char imxrt_memory_flexspi_end[];
+extern char imxrt_memory_flexspi_size[];
+
+extern char imxrt_memory_flexspi_fifo_begin[];
+extern char imxrt_memory_flexspi_fifo_end[];
+extern char imxrt_memory_flexspi_fifo_size[];
+
+extern char imxrt_memory_sdram_begin[];
+extern char imxrt_memory_sdram_end[];
+extern char imxrt_memory_sdram_size[];
+
+extern char imxrt_memory_sdram_nocache_begin[];
+extern char imxrt_memory_sdram_nocache_end[];
+extern char imxrt_memory_sdram_nocache_size[];
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LIBBSP_ARM_IMXRT_IMXRT_MEMORY_H */
diff --git a/bsps/arm/imxrt/include/tm27.h b/bsps/arm/imxrt/include/tm27.h
new file mode 100644
index 0000000000..0dfa7bf628
--- /dev/null
+++ b/bsps/arm/imxrt/include/tm27.h
@@ -0,0 +1 @@
+#include <rtems/tm27-default.h>
diff --git a/bsps/arm/imxrt/spi/imxrt-lpspi.c b/bsps/arm/imxrt/spi/imxrt-lpspi.c
new file mode 100644
index 0000000000..02a6859521
--- /dev/null
+++ b/bsps/arm/imxrt/spi/imxrt-lpspi.c
@@ -0,0 +1,532 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <bsp.h>
+#include <bsp/fatal.h>
+#include <bsp/fdt.h>
+#include <bsp/irq.h>
+
+#include <chip.h>
+#include <dev/spi/spi.h>
+#include <fsl_clock.h>
+#include <libfdt.h>
+
+struct imxrt_lpspi_bus {
+ spi_bus base;
+ volatile LPSPI_Type *regs;
+ rtems_vector_number irq;
+ uint32_t src_clock_hz;
+ clock_ip_name_t clock_ip;
+
+ uint32_t msg_todo;
+ const spi_ioc_transfer *msg;
+ rtems_id task_id;
+ uint32_t tcr;
+
+ size_t remaining_rx_size;
+ uint8_t *rx_buf;
+
+ size_t remaining_tx_size;
+ const uint8_t *tx_buf;
+ uint32_t fifo_size;
+};
+
+static const uint32_t word_size = 8;
+
+static unsigned div_round_up(unsigned divident, unsigned divisor)
+{
+ return (divident + divisor - 1) / divisor;
+}
+
+static void imxrt_lpspi_find_clockdivs(
+ struct imxrt_lpspi_bus *bus,
+ uint32_t max_baud_hz,
+ unsigned *sckdiv,
+ unsigned *prescale
+)
+{
+ const unsigned max_sckdif = LPSPI_CCR_SCKDIV_MASK >> LPSPI_CCR_SCKDIV_SHIFT;
+ const unsigned max_prescale =
+ LPSPI_TCR_PRESCALE_MASK >> LPSPI_TCR_PRESCALE_SHIFT;
+
+ unsigned best_baud_hz;
+ int best_sckdif;
+ int best_prescale;
+
+ int check_baud_hz;
+ int check_sckdif;
+ int check_prescale;
+
+ /* Start with slowest possible */
+ best_sckdif = max_sckdif;
+ best_prescale = max_prescale;
+ best_baud_hz = div_round_up(bus->src_clock_hz,
+ (1 << best_prescale) * (best_sckdif + 2));
+
+ for (check_prescale = 0;
+ check_prescale <= max_prescale && best_baud_hz < max_baud_hz;
+ ++check_prescale) {
+
+ check_sckdif = div_round_up(bus->src_clock_hz,
+ (1 << check_prescale) * max_baud_hz) - 2;
+
+ if (check_sckdif > max_sckdif) {
+ check_sckdif = max_sckdif;
+ }
+
+ check_baud_hz = div_round_up(bus->src_clock_hz,
+ (1 << check_prescale) * (check_sckdif + 2));
+
+ if (check_baud_hz <= max_baud_hz && check_baud_hz > best_baud_hz) {
+ best_baud_hz = check_baud_hz;
+ best_sckdif = check_sckdif;
+ best_prescale = check_prescale;
+ }
+ }
+
+ *sckdiv = best_sckdif;
+ *prescale = best_prescale;
+}
+
+static void imxrt_lpspi_config(
+ struct imxrt_lpspi_bus *bus,
+ volatile LPSPI_Type *regs,
+ const spi_ioc_transfer *msg
+)
+{
+ uint32_t ccr_orig;
+ uint32_t ccr;
+ uint32_t tcr;
+ unsigned sckdiv;
+ unsigned prescale;
+
+ ccr_orig = ccr = regs->CCR;
+ tcr = 0;
+
+ imxrt_lpspi_find_clockdivs(bus, msg->speed_hz, &sckdiv, &prescale);
+
+ /* Currently just force half a clock after and before chip select. */
+ ccr = LPSPI_CCR_SCKDIV(sckdiv) | LPSPI_CCR_SCKPCS(sckdiv) |
+ LPSPI_CCR_PCSSCK(sckdiv) | LPSPI_CCR_DBT(sckdiv);
+ tcr |= LPSPI_TCR_PRESCALE(prescale);
+
+ if ((msg->mode & SPI_CPOL) != 0) {
+ tcr |= LPSPI_TCR_CPOL_MASK;
+ }
+ if ((msg->mode & SPI_CPHA) != 0) {
+ tcr |= LPSPI_TCR_CPHA_MASK;
+ }
+ if (msg->mode & SPI_LSB_FIRST) {
+ tcr |= LPSPI_TCR_LSBF_MASK;
+ }
+
+ tcr |= LPSPI_TCR_PCS(msg->cs);
+
+ if (!msg->cs_change) {
+ tcr |= LPSPI_TCR_CONT_MASK;
+ }
+
+ tcr |= LPSPI_TCR_FRAMESZ(word_size-1);
+
+ if (ccr_orig != ccr) {
+ regs->CR &= ~LPSPI_CR_MEN_MASK;
+ regs->CCR = ccr;
+ regs->CR |= LPSPI_CR_MEN_MASK;
+ }
+
+ /* No CONTC on first write. Otherwise upper 8 bits are not written. */
+ regs->TCR = tcr;
+ regs->TCR = tcr | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_CONT_MASK;
+}
+
+static inline bool imxrt_lpspi_rx_fifo_not_empty(
+ volatile LPSPI_Type *regs
+)
+{
+ return ((regs->RSR & LPSPI_RSR_RXEMPTY_MASK) == 0);
+}
+
+static inline bool imxrt_lpspi_tx_fifo_not_full(
+ struct imxrt_lpspi_bus *bus,
+ volatile LPSPI_Type *regs
+)
+{
+ /*
+ * We might add two things to the FIFO: A TCR and data. Therefore leave one
+ * extra space.
+ */
+ return ((regs->FSR & LPSPI_FSR_TXCOUNT_MASK) >> LPSPI_FSR_TXCOUNT_SHIFT) <
+ bus->fifo_size - 2;
+}
+
+static void imxrt_lpspi_fill_tx_fifo(
+ struct imxrt_lpspi_bus *bus,
+ volatile LPSPI_Type *regs
+)
+{
+ while(imxrt_lpspi_tx_fifo_not_full(bus, regs)
+ && bus->remaining_tx_size > 0) {
+ if (bus->remaining_tx_size == 1) {
+ regs->TCR &= ~(LPSPI_TCR_CONT_MASK);
+ }
+
+ if (bus->tx_buf != NULL) {
+ regs->TDR = bus->tx_buf[0];
+ ++bus->tx_buf;
+ } else {
+ regs->TDR = 0;
+ }
+ --bus->remaining_tx_size;
+ }
+}
+
+static void imxrt_lpspi_next_msg(
+ struct imxrt_lpspi_bus *bus,
+ volatile LPSPI_Type *regs
+)
+{
+ if (bus->msg_todo > 0) {
+ const spi_ioc_transfer *msg;
+
+ msg = bus->msg;
+
+ imxrt_lpspi_config(bus, regs, msg);
+ bus->remaining_tx_size = msg->len;
+ bus->remaining_rx_size = msg->len;
+ bus->rx_buf = msg->rx_buf;
+ bus->tx_buf = msg->tx_buf;
+
+ imxrt_lpspi_fill_tx_fifo(bus, regs);
+ regs->IER = LPSPI_IER_TDIE_MASK;
+ } else {
+ regs->IER = 0;
+ rtems_event_transient_send(bus->task_id);
+ }
+}
+
+static void imxrt_lpspi_pull_data_from_rx_fifo(
+ struct imxrt_lpspi_bus *bus,
+ volatile LPSPI_Type *regs
+)
+{
+ while (imxrt_lpspi_rx_fifo_not_empty(regs) && bus->remaining_rx_size > 0) {
+ uint32_t data;
+
+ data = regs->RDR;
+ if (bus->rx_buf != NULL) {
+ *bus->rx_buf = data;
+ ++bus->rx_buf;
+ }
+ --bus->remaining_rx_size;
+ }
+}
+
+static void imxrt_lpspi_interrupt(void *arg)
+{
+ struct imxrt_lpspi_bus *bus;
+ volatile LPSPI_Type *regs;
+
+ bus = arg;
+ regs = bus->regs;
+
+ imxrt_lpspi_pull_data_from_rx_fifo(bus, regs);
+ imxrt_lpspi_fill_tx_fifo(bus, regs);
+
+ if (bus->remaining_tx_size == 0) {
+ if (bus->remaining_rx_size > 0) {
+ regs->IER = LPSPI_IER_RDIE_MASK;
+ } else {
+ --bus->msg_todo;
+ ++bus->msg;
+ imxrt_lpspi_next_msg(bus, regs);
+ }
+ }
+}
+
+static inline int imxrt_lpspi_settings_ok(
+ struct imxrt_lpspi_bus *bus,
+ const spi_ioc_transfer *msg
+)
+{
+ if (msg->cs_change == 0) {
+ /*
+ * This one most likely would need a bigger workaround if it is necessary.
+ * See "i.MX RT1050 Processor Reference Manual Rev. 4" Chapter 47.3.2.2
+ * "Receive FIFO and Data Match":
+ *
+ * "During a continuous transfer, if the transmit FIFO is empty, then the
+ * receive data is only written to the receive FIFO after the transmit FIFO
+ * is written or after the Transmit Command Register (TCR) is written to end
+ * the frame."
+ *
+ * It might is possible to extend the driver so that it can work with an
+ * empty read buffer.
+ */
+ return -EINVAL;
+ }
+
+ /* most of this is currently just not implemented */
+ if (msg->cs > 3 ||
+ msg->speed_hz > bus->base.max_speed_hz ||
+ msg->delay_usecs != 0 ||
+ (msg->mode & ~(SPI_CPHA | SPI_CPOL | SPI_LSB_FIRST)) != 0 ||
+ msg->bits_per_word != word_size) {
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int imxrt_lpspi_check_messages(
+ struct imxrt_lpspi_bus *bus,
+ const spi_ioc_transfer *msg,
+ uint32_t size
+)
+{
+ while(size > 0) {
+ int rv;
+ rv = imxrt_lpspi_settings_ok(bus, msg);
+ if (rv != 0) {
+ return rv;
+ }
+
+ ++msg;
+ --size;
+ }
+
+ return 0;
+}
+
+static int imxrt_lpspi_transfer(
+ spi_bus *base,
+ const spi_ioc_transfer *msgs,
+ uint32_t n
+)
+{
+ struct imxrt_lpspi_bus *bus;
+ int rv;
+
+ bus = (struct imxrt_lpspi_bus *) base;
+
+ rv = imxrt_lpspi_check_messages(bus, msgs, n);
+
+ if (rv == 0) {
+ bus->msg_todo = n;
+ bus->msg = &msgs[0];
+ bus->task_id = rtems_task_self();
+
+ imxrt_lpspi_next_msg(bus, bus->regs);
+ rtems_event_transient_receive(RTEMS_WAIT, RTEMS_NO_TIMEOUT);
+ }
+
+ return rv;
+}
+
+static void imxrt_lpspi_sw_reset(volatile LPSPI_Type *regs)
+{
+ regs->CR = LPSPI_CR_RST_MASK | LPSPI_CR_RRF_MASK | LPSPI_CR_RTF_MASK;
+ regs->CR = 0;
+}
+
+static void imxrt_lpspi_destroy(spi_bus *base)
+{
+ struct imxrt_lpspi_bus *bus;
+ volatile LPSPI_Type *regs;
+
+ bus = (struct imxrt_lpspi_bus *) base;
+ regs = bus->regs;
+ imxrt_lpspi_sw_reset(regs);
+
+ CLOCK_DisableClock(bus->clock_ip);
+
+ rtems_interrupt_handler_remove(bus->irq, imxrt_lpspi_interrupt, bus);
+ spi_bus_destroy_and_free(&bus->base);
+}
+
+static int imxrt_lpspi_hw_init(struct imxrt_lpspi_bus *bus)
+{
+ rtems_status_code sc;
+ volatile LPSPI_Type *regs;
+
+ regs = bus->regs;
+
+ CLOCK_EnableClock(bus->clock_ip);
+
+ imxrt_lpspi_sw_reset(regs);
+
+ regs->CFGR1 |= LPSPI_CFGR1_MASTER_MASK;
+ regs->FCR = LPSPI_FCR_TXWATER(0) | LPSPI_FCR_RXWATER(0);
+ regs->CR |= LPSPI_CR_MEN_MASK;
+
+ bus->fifo_size = 1 << ((regs->PARAM & LPSPI_PARAM_TXFIFO_MASK) >>
+ LPSPI_PARAM_TXFIFO_SHIFT);
+
+ sc = rtems_interrupt_handler_install(
+ bus->irq,
+ "LPSPI",
+ RTEMS_INTERRUPT_UNIQUE,
+ imxrt_lpspi_interrupt,
+ bus
+ );
+ if (sc != RTEMS_SUCCESSFUL) {
+ return EAGAIN;
+ }
+
+ return 0;
+}
+
+static int imxrt_lpspi_setup(spi_bus *base)
+{
+ struct imxrt_lpspi_bus *bus;
+ int rv;
+ spi_ioc_transfer msg = {
+ .cs_change = base->cs_change,
+ .cs = base->cs,
+ .bits_per_word = base->bits_per_word,
+ .mode = base->mode,
+ .speed_hz = base->speed_hz,
+ .delay_usecs = base->delay_usecs,
+ .rx_buf = NULL,
+ .tx_buf = NULL,
+ };
+
+ bus = (struct imxrt_lpspi_bus *) base;
+
+ rv = imxrt_lpspi_settings_ok(bus, &msg);
+
+ /*
+ * Nothing to do besides checking.
+ * Every transfer will later overwrite the settings anyway.
+ */
+
+ return rv;
+}
+
+static uint32_t imxrt_lpspi_get_src_freq(void)
+{
+ uint32_t freq;
+ uint32_t mux;
+ uint32_t divider;
+
+ mux = CLOCK_GetMux(kCLOCK_LpspiMux);
+
+ switch (mux) {
+ case 0: /* PLL3 PFD1 */
+ freq = CLOCK_GetFreq(kCLOCK_Usb1PllPfd1Clk);
+ break;
+ case 1: /* PLL3 PFD0 */
+ freq = CLOCK_GetFreq(kCLOCK_Usb1PllPfd0Clk);
+ break;
+ case 2: /* PLL2 */
+ freq = CLOCK_GetFreq(kCLOCK_SysPllClk);
+ break;
+ case 3: /* PLL2 PFD2 */
+ freq = CLOCK_GetFreq(kCLOCK_SysPllPfd2Clk);
+ break;
+ default:
+ freq = 0;
+ }
+
+ divider = CLOCK_GetDiv(kCLOCK_LpspiDiv) + 1;
+ freq /= divider;
+
+ return freq;
+}
+
+static clock_ip_name_t imxrt_lpspi_clock_ip(volatile LPSPI_Type *regs)
+{
+ LPSPI_Type *const base_addresses[] = LPSPI_BASE_PTRS;
+ static const clock_ip_name_t lpspi_clocks[] = LPSPI_CLOCKS;
+ size_t i;
+
+ for (i = 0; i < RTEMS_ARRAY_SIZE(base_addresses); ++i) {
+ if (base_addresses[i] == regs) {
+ return lpspi_clocks[i];
+ }
+ }
+
+ return kCLOCK_IpInvalid;
+}
+
+void imxrt_lpspi_init(void)
+{
+ const void *fdt;
+ int node;
+
+ fdt = bsp_fdt_get();
+ node = -1;
+
+ do {
+ node = fdt_node_offset_by_compatible(fdt, node, "nxp,imxrt-lpspi");
+
+ if (node >= 0 && imxrt_fdt_node_is_enabled(fdt, node)) {
+ struct imxrt_lpspi_bus *bus;
+ int eno;
+ const char *bus_path;
+
+ bus = (struct imxrt_lpspi_bus*) spi_bus_alloc_and_init(sizeof(*bus));
+ if (bus == NULL) {
+ bsp_fatal(IMXRT_FATAL_LPSPI_ALLOC_FAILED);
+ }
+
+ bus->regs = imx_get_reg_of_node(fdt, node);
+ if (bus->regs == NULL) {
+ bsp_fatal(IMXRT_FATAL_LPSPI_INVALID_FDT);
+ }
+
+ bus->irq = imx_get_irq_of_node(fdt, node, 0);
+ if (bus->irq == BSP_INTERRUPT_VECTOR_INVALID) {
+ bsp_fatal(IMXRT_FATAL_LPSPI_INVALID_FDT);
+ }
+
+ bus_path = fdt_getprop(fdt, node, "rtems,path", NULL);
+ if (bus_path == NULL) {
+ bsp_fatal(IMXRT_FATAL_LPSPI_INVALID_FDT);
+ }
+
+ bus->clock_ip = imxrt_lpspi_clock_ip(bus->regs);
+ bus->src_clock_hz = imxrt_lpspi_get_src_freq();
+ /* Absolut maximum is 30MHz according to electrical characteristics */
+ bus->base.max_speed_hz = MIN(bus->src_clock_hz / 2, 30000000);
+ bus->base.delay_usecs = 0;
+
+ eno = imxrt_lpspi_hw_init(bus);
+ if (eno != 0) {
+ bsp_fatal(IMXRT_FATAL_LPSPI_HW_INIT_FAILED);
+ }
+
+ bus->base.transfer = imxrt_lpspi_transfer;
+ bus->base.destroy = imxrt_lpspi_destroy;
+ bus->base.setup = imxrt_lpspi_setup;
+
+ eno = spi_bus_register(&bus->base, bus_path);
+ if (eno != 0) {
+ bsp_fatal(IMXRT_FATAL_LPSPI_REGISTER_FAILED);
+ }
+ }
+ } while (node >= 0);
+}
diff --git a/bsps/arm/imxrt/start/bspstart.c b/bsps/arm/imxrt/start/bspstart.c
new file mode 100644
index 0000000000..884f0aaf92
--- /dev/null
+++ b/bsps/arm/imxrt/start/bspstart.c
@@ -0,0 +1,141 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <rtems/sysinit.h>
+
+#include <bsp.h>
+#include <bsp/bootcard.h>
+#include <bsp/fdt.h>
+#include <bsp/imx-iomux.h>
+#include <bsp/irq-generic.h>
+#include <bsp/irq.h>
+#include <bsp/linker-symbols.h>
+#include <bsp/flash-headers.h>
+
+#include <fsl_clock.h>
+#include <libfdt.h>
+
+uint32_t imxrt_systick_frequency(void)
+{
+ return CLOCK_GetCpuClkFreq();
+}
+
+static void imxrt_disable_wait_mode(void)
+{
+ /*
+ * Prevent processor from entering WAIT or SLEEP mode when a WFI is executed.
+ * This would switch off the normal interrupt controller and activate an
+ * alternative one. See "i.MX RT1050 Reference Manual, Rev. 4, 12/2019"
+ * chapter 14.6.3.2.1 "Entering WAIT mode".
+ *
+ * FIXME: For saving energy it would be a better solution to support the
+ * alternative interrupt controller. But that makes a bit of work necessary on
+ * every WFI.
+ */
+ CLOCK_SetMode(kCLOCK_ModeRun);
+}
+
+void bsp_start(void)
+{
+ imxrt_disable_wait_mode();
+
+ bsp_interrupt_initialize();
+ rtems_cache_coherent_add_area(
+ bsp_section_nocacheheap_begin,
+ (uintptr_t) bsp_section_nocacheheap_size
+ );
+}
+
+const void *bsp_fdt_get(void)
+{
+ return imxrt_dtb;
+}
+
+bool imxrt_fdt_node_is_enabled(const void *fdt, int node)
+{
+ int len;
+ const uint32_t *val;
+
+ val = fdt_getprop(fdt, node, "status", &len);
+ if (val != NULL &&
+ (strcmp((char*)val, "ok") == 0 || strcmp((char*)val, "okay") == 0)) {
+ return true;
+ }
+
+ return false;
+}
+
+void *imx_get_reg_of_node(const void *fdt, int node)
+{
+ int len;
+ const uint32_t *val;
+
+ val = fdt_getprop(fdt, node, "reg", &len);
+ if (val == NULL || len < 4) {
+ return NULL;
+ }
+
+ return (void *) fdt32_to_cpu(val[0]);
+}
+
+rtems_vector_number imx_get_irq_of_node(
+ const void *fdt,
+ int node,
+ size_t index
+)
+{
+ int len;
+ const uint32_t *val;
+
+ val = fdt_getprop(fdt, node, "interrupts", &len);
+ if (val == NULL || len < (int) ((index) * 4)) {
+ return BSP_INTERRUPT_VECTOR_INVALID;
+ }
+
+ return fdt32_to_cpu(val[index]);
+}
+
+uint32_t bsp_fdt_map_intr(const uint32_t *intr, size_t icells)
+{
+ return intr[0];
+}
+
+/* Make sure to pull in the flash headers */
+__attribute__((used)) static const void *hdr_dcd = &imxrt_dcd_data;
+__attribute__((used)) static const void *hdr_ivt = &imxrt_image_vector_table;
+__attribute__((used)) static const void *hdr_btd = &imxrt_boot_data;
+__attribute__((used)) static const void *hdr_fsc = &imxrt_flexspi_config;
+
+/* pull in some drivers */
+__attribute__((used)) static const void *drv_iomux = &imx_iomux_configure_pins;
+
+RTEMS_SYSINIT_ITEM(imxrt_lpspi_init, RTEMS_SYSINIT_DEVICE_DRIVERS,
+ RTEMS_SYSINIT_ORDER_MIDDLE);
+RTEMS_SYSINIT_ITEM(imxrt_lpi2c_init, RTEMS_SYSINIT_DEVICE_DRIVERS,
+ RTEMS_SYSINIT_ORDER_MIDDLE);
+RTEMS_SYSINIT_ITEM(imxrt_ffec_init, RTEMS_SYSINIT_DEVICE_DRIVERS,
+ RTEMS_SYSINIT_ORDER_MIDDLE);
diff --git a/bsps/arm/imxrt/start/bspstarthooks.c b/bsps/arm/imxrt/start/bspstarthooks.c
new file mode 100644
index 0000000000..7b220a493b
--- /dev/null
+++ b/bsps/arm/imxrt/start/bspstarthooks.c
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2013, 2018 embedded brains GmbH. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Dornierstr. 4
+ * 82178 Puchheim
+ * Germany
+ * <info at embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#include <rtems/score/armv7m.h>
+
+#include <bsp.h>
+#include <bsp/fatal.h>
+#include <bsp/start.h>
+
+#include <chip.h>
+#include <fsl_pin_mux.h>
+#include <fsl_clock_config.h>
+#include <imxrt/memory.h>
+
+static void init_mpu(void)
+{
+ volatile ARMV7M_MPU *mpu;
+ volatile ARMV7M_SCB *scb;
+ uint32_t region_count;
+ uint32_t region;
+
+ mpu = _ARMV7M_MPU;
+ scb = _ARMV7M_SCB;
+
+ region_count = ARMV7M_MPU_TYPE_DREGION_GET(mpu->type);
+
+ for (region = 0; region < region_count; ++region) {
+ mpu->rbar = ARMV7M_MPU_RBAR_VALID | region;
+ mpu->rasr = 0;
+ }
+
+ _ARMV7M_MPU_set_region(
+ mpu,
+ 0,
+ ARMV7M_MPU_RASR_AP(0x3)
+ | ARMV7M_MPU_RASR_TEX(0x1) | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_B
+ | ARMV7M_MPU_RASR_ENABLE,
+ imxrt_memory_sdram_begin,
+ imxrt_memory_sdram_end
+ );
+ _ARMV7M_MPU_set_region(
+ mpu,
+ 1,
+ ARMV7M_MPU_RASR_AP(0x3)
+ | ARMV7M_MPU_RASR_TEX(0x1) | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_B
+ | ARMV7M_MPU_RASR_ENABLE,
+ imxrt_memory_ocram_begin,
+ imxrt_memory_ocram_end
+ );
+ _ARMV7M_MPU_set_region(
+ mpu,
+ 2,
+ ARMV7M_MPU_RASR_AP(0x3)
+ | ARMV7M_MPU_RASR_TEX(0x1) | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_B
+ | ARMV7M_MPU_RASR_ENABLE,
+ imxrt_memory_flexspi_config_begin,
+ imxrt_memory_flexspi_end
+ );
+ _ARMV7M_MPU_set_region(
+ mpu,
+ 3,
+ ARMV7M_MPU_RASR_AP(0x3)
+ | ARMV7M_MPU_RASR_TEX(0x2)
+ | ARMV7M_MPU_RASR_ENABLE,
+ imxrt_memory_sdram_nocache_begin,
+ imxrt_memory_sdram_nocache_end
+ );
+ _ARMV7M_MPU_set_region(
+ mpu,
+ 4,
+ ARMV7M_MPU_RASR_XN
+ | ARMV7M_MPU_RASR_AP(0x3)
+ | ARMV7M_MPU_RASR_TEX(0x2)
+ | ARMV7M_MPU_RASR_ENABLE,
+ imxrt_memory_peripheral_begin,
+ imxrt_memory_peripheral_end
+ );
+ _ARMV7M_MPU_set_region(
+ mpu,
+ region_count - 1,
+ ARMV7M_MPU_RASR_XN
+ | ARMV7M_MPU_RASR_AP(0x0)
+ | ARMV7M_MPU_RASR_ENABLE,
+ imxrt_memory_null_begin,
+ imxrt_memory_null_end
+ );
+
+ mpu->ctrl = ARMV7M_MPU_CTRL_ENABLE | ARMV7M_MPU_CTRL_PRIVDEFENA;
+ scb->shcsr |= ARMV7M_SCB_SHCSR_MEMFAULTENA;
+
+ _ARM_Data_synchronization_barrier();
+ _ARM_Instruction_synchronization_barrier();
+}
+
+BSP_START_TEXT_SECTION void bsp_start_hook_0(void)
+{
+ /* FIXME: Initializing SDRAM is currently done by DCD. It would be more user
+ * friendly if that would be done here with a readable structure. */
+ if ((SCB->CCR & SCB_CCR_IC_Msk) == 0) {
+ SCB_EnableICache();
+ }
+
+ if ((SCB->CCR & SCB_CCR_DC_Msk) == 0) {
+ SCB_EnableDCache();
+ }
+
+ init_mpu();
+}
+
+BSP_START_TEXT_SECTION void bsp_start_hook_1(void)
+{
+ bsp_start_copy_sections_compact();
+ SCB_CleanDCache();
+ SCB_InvalidateICache();
+ bsp_start_clear_bss();
+
+ BOARD_BootClockRUN();
+ BOARD_InitDEBUG_UARTPins();
+
+ /* Reduce frequency for I2C */
+ CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 5);
+}
diff --git a/bsps/arm/imxrt/start/flash-boot-data.c b/bsps/arm/imxrt/start/flash-boot-data.c
new file mode 100644
index 0000000000..cf0430af72
--- /dev/null
+++ b/bsps/arm/imxrt/start/flash-boot-data.c
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <bsp/flash-headers.h>
+#include <imxrt/memory.h>
+#include <bspopts.h>
+
+const BOOT_DATA_T imxrt_boot_data = {
+ .start = (uint32_t) imxrt_memory_flexspi_config_begin,
+ .size = IMXRT_MEMORY_FLEXSPI_FLASH_SIZE,
+ .plugin = PLUGIN_FLAG,
+ .placeholder = 0xFFFFFFFF,
+};
diff --git a/bsps/arm/imxrt/start/flash-config.c b/bsps/arm/imxrt/start/flash-config.c
new file mode 100644
index 0000000000..07324f1330
--- /dev/null
+++ b/bsps/arm/imxrt/start/flash-config.c
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <bsp/flash-headers.h>
+#include <bspopts.h>
+
+const flexspi_nor_config_t imxrt_flexspi_config = {
+ .memConfig = {
+ .tag = FLEXSPI_CFG_BLK_TAG,
+ .version = FLEXSPI_CFG_BLK_VERSION,
+ .readSampleClkSrc = kFlexSPIReadSampleClk_ExternalInputFromDqsPad,
+ .csHoldTime = 3u,
+ .csSetupTime = 3u,
+ .columnAddressWidth = 3u,
+ .controllerMiscOption = (1 << kFlexSpiMiscOffset_DdrModeEnable) |
+ (1 << kFlexSpiMiscOffset_WordAddressableEnable) |
+ (1 << kFlexSpiMiscOffset_SafeConfigFreqEnable) |
+ (1 << kFlexSpiMiscOffset_DiffClkEnable),
+ .deviceType = kFlexSpiDeviceType_SerialRAM,
+ .sflashPadType = kSerialFlash_8Pads,
+ .serialClkFreq = kFlexSpiSerialClk_133MHz,
+ .sflashA1Size = IMXRT_MEMORY_FLEXSPI_FLASH_SIZE,
+ .dataValidTime = {16u, 16u},
+ .lookupTable = {
+ FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0xA0, RADDR_DDR, FLEXSPI_8PAD, 0x18),
+ FLEXSPI_LUT_SEQ(CADDR_DDR, FLEXSPI_8PAD, 0x10, DUMMY_DDR, FLEXSPI_8PAD, 0x06),
+ FLEXSPI_LUT_SEQ(READ_DDR, FLEXSPI_8PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0),
+ },
+ .lutCustomSeq = {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
+ {0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ },
+ .pageSize = 0x200,
+ .sectorSize = 0x40000,
+ .blockSize = 0x40000,
+ .isUniformBlockSize = 1,
+};
diff --git a/bsps/arm/imxrt/start/flash-dcd.c b/bsps/arm/imxrt/start/flash-dcd.c
index 6dced830b9..a53e5bda39 100644
--- a/bsps/arm/imxrt/start/flash-dcd.c
+++ b/bsps/arm/imxrt/start/flash-dcd.c
@@ -5,38 +5,11 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-/***********************************************************************************************************************
- * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
- * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
- **********************************************************************************************************************/
+#include <bsp/flash-headers.h>
+#include <stdint.h>
-#include "dcd.h"
-
-/* Component ID definition, used by tools. */
-#ifndef FSL_COMPONENT_ID
-#define FSL_COMPONENT_ID "platform.drivers.xip_board"
-#endif
-
-#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
-#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
-#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
__attribute__((section(".boot_hdr.dcd_data")))
-#elif defined(__ICCARM__)
-#pragma location = ".boot_hdr.dcd_data"
-#endif
-
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!GlobalInfo
-product: DCDx V2.0
-processor: MIMXRT1052xxxxB
-package_id: MIMXRT1052DVL6B
-mcu_data: ksdk2_0
-processor_version: 0.0.0
-board: IMXRT1050-EVKB
-output_format: c_array
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */
-const uint8_t dcd_data[] = {
+const uint8_t imxrt_dcd_data[] = {
/* HEADER */
/* Tag */
0xD2,
@@ -308,8 +281,3 @@ const uint8_t dcd_data[] = {
0xCC, 0x00, 0x0C, 0x04, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x09
};
/* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */
-
-#else
-const uint8_t dcd_data[] = {0x00};
-#endif /* XIP_BOOT_HEADER_DCD_ENABLE */
-#endif /* XIP_BOOT_HEADER_ENABLE */
diff --git a/bsps/arm/imxrt/start/flash-ivt.c b/bsps/arm/imxrt/start/flash-ivt.c
new file mode 100644
index 0000000000..fd396d5e1a
--- /dev/null
+++ b/bsps/arm/imxrt/start/flash-ivt.c
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <bsp/flash-headers.h>
+#include <bspopts.h>
+
+void _start(void);
+
+const ivt imxrt_image_vector_table = {
+ .hdr = IVT_HEADER,
+ .entry = (uint32_t) _start - 1, /* remove thumb mode flag! */
+ .dcd = (uint32_t) &imxrt_dcd_data,
+ .boot_data = (uint32_t) &imxrt_boot_data,
+ .self = (uint32_t) &imxrt_image_vector_table,
+};
diff --git a/bsps/arm/imxrt/start/imxrt-ffec-init.c b/bsps/arm/imxrt/start/imxrt-ffec-init.c
new file mode 100644
index 0000000000..4b71944c00
--- /dev/null
+++ b/bsps/arm/imxrt/start/imxrt-ffec-init.c
@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <bsp.h>
+#include <bsp/fdt.h>
+#include <bsp/imx-gpio.h>
+#include <chip.h>
+#include <fsl_clock.h>
+#include <libfdt.h>
+#include <rtems/counter.h>
+
+void imxrt_ffec_init(void)
+{
+ volatile IOMUXC_GPR_Type *iomuxc_gpr = IOMUXC_GPR;
+ const void *fdt;
+ int node;
+
+ fdt = bsp_fdt_get();
+
+ const clock_enet_pll_config_t config = {
+ .enableClkOutput = true,
+ .enableClkOutput25M = false,
+ .loopDivider = 1
+ };
+
+ CLOCK_InitEnetPll(&config);
+
+ iomuxc_gpr->GPR1 |= IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
+
+ node = fdt_node_offset_by_compatible(fdt, -1, "fsl,imxrt-fec");
+ if (node >= 0) {
+ struct imx_gpio_pin reset;
+ struct imx_gpio_pin interrupt;
+ rtems_status_code sc;
+
+ sc = imx_gpio_init_from_fdt_property(
+ &reset, node, "phy-reset-gpios",
+ IMX_GPIO_MODE_OUTPUT, 0);
+
+ if (sc == RTEMS_SUCCESSFUL) {
+ sc = imx_gpio_init_from_fdt_property(
+ &interrupt, node, "rtems,phy-interrupt-gpios",
+ IMX_GPIO_MODE_INPUT, 0);
+
+ imx_gpio_set_output(&reset, 0);
+ if (sc == RTEMS_SUCCESSFUL) {
+ /* Force interrupt GPIO to high. Otherwise we
+ * get NAND_TREE mode of the PHY. */
+ interrupt.mode = IMX_GPIO_MODE_OUTPUT;
+ imx_gpio_init(&interrupt);
+ imx_gpio_set_output(&interrupt, 1);
+ }
+ rtems_counter_delay_nanoseconds(100000);
+ imx_gpio_set_output(&reset, 1);
+ rtems_counter_delay_nanoseconds(5);
+ if (sc == RTEMS_SUCCESSFUL) {
+ interrupt.mode = IMX_GPIO_MODE_INPUT;
+ imx_gpio_init(&interrupt);
+ }
+ }
+ }
+}
diff --git a/bsps/arm/imxrt/start/linkcmds.flexspi b/bsps/arm/imxrt/start/linkcmds.flexspi
new file mode 100644
index 0000000000..4196bb33e5
--- /dev/null
+++ b/bsps/arm/imxrt/start/linkcmds.flexspi
@@ -0,0 +1,35 @@
+INCLUDE linkcmds.memory
+
+REGION_ALIAS ("REGION_START", FLEXSPI);
+REGION_ALIAS ("REGION_VECTOR", FLEXSPI);
+REGION_ALIAS ("REGION_TEXT", FLEXSPI);
+REGION_ALIAS ("REGION_TEXT_LOAD", FLEXSPI);
+REGION_ALIAS ("REGION_RODATA", FLEXSPI);
+REGION_ALIAS ("REGION_RODATA_LOAD", FLEXSPI);
+REGION_ALIAS ("REGION_DATA", SDRAM);
+REGION_ALIAS ("REGION_DATA_LOAD", FLEXSPI);
+REGION_ALIAS ("REGION_FAST_TEXT", FLEXSPI);
+REGION_ALIAS ("REGION_FAST_TEXT_LOAD", FLEXSPI);
+REGION_ALIAS ("REGION_FAST_DATA", SDRAM);
+REGION_ALIAS ("REGION_FAST_DATA_LOAD", FLEXSPI);
+REGION_ALIAS ("REGION_BSS", SDRAM);
+REGION_ALIAS ("REGION_WORK", SDRAM);
+REGION_ALIAS ("REGION_STACK", SDRAM);
+REGION_ALIAS ("REGION_NOCACHE", SDRAM_NOCACHE);
+REGION_ALIAS ("REGION_NOCACHE_LOAD", FLEXSPI);
+
+bsp_vector_table_in_start_section = 1;
+
+SECTIONS {
+ . = imxrt_memory_flexspi_begin;
+ .flash_config : ALIGN_WITH_INPUT {
+ KEEP(*(.boot_hdr.conf))
+ } > FLEXSPI_CONFIG AT > FLEXSPI_CONFIG
+ .flash_ivt : ALIGN_WITH_INPUT {
+ KEEP(*(.boot_hdr.ivt))
+ KEEP(*(.boot_hdr.boot_data))
+ KEEP(*(.boot_hdr.dcd_data))
+ } > FLEXSPI_IVT AT > FLEXSPI_IVT
+}
+
+INCLUDE linkcmds.armv7m
diff --git a/bsps/arm/imxrt/start/linkcmds.sdram b/bsps/arm/imxrt/start/linkcmds.sdram
new file mode 100644
index 0000000000..87d1dffa53
--- /dev/null
+++ b/bsps/arm/imxrt/start/linkcmds.sdram
@@ -0,0 +1,23 @@
+INCLUDE linkcmds.memory
+
+REGION_ALIAS ("REGION_START", SDRAM);
+REGION_ALIAS ("REGION_VECTOR", SDRAM);
+REGION_ALIAS ("REGION_TEXT", SDRAM);
+REGION_ALIAS ("REGION_TEXT_LOAD", SDRAM);
+REGION_ALIAS ("REGION_RODATA", SDRAM);
+REGION_ALIAS ("REGION_RODATA_LOAD", SDRAM);
+REGION_ALIAS ("REGION_DATA", SDRAM);
+REGION_ALIAS ("REGION_DATA_LOAD", SDRAM);
+REGION_ALIAS ("REGION_FAST_TEXT", SDRAM);
+REGION_ALIAS ("REGION_FAST_TEXT_LOAD", SDRAM);
+REGION_ALIAS ("REGION_FAST_DATA", SDRAM);
+REGION_ALIAS ("REGION_FAST_DATA_LOAD", SDRAM);
+REGION_ALIAS ("REGION_BSS", SDRAM);
+REGION_ALIAS ("REGION_WORK", SDRAM);
+REGION_ALIAS ("REGION_STACK", SDRAM);
+REGION_ALIAS ("REGION_NOCACHE", SDRAM_NOCACHE);
+REGION_ALIAS ("REGION_NOCACHE_LOAD", SDRAM);
+
+bsp_vector_table_in_start_section = 1;
+
+INCLUDE linkcmds.armv7m
diff --git a/bsps/arm/shared/pins/imx_iomux.c b/bsps/arm/shared/pins/imx_iomux.c
index d97e35deef..1ff4186360 100644
--- a/bsps/arm/shared/pins/imx_iomux.c
+++ b/bsps/arm/shared/pins/imx_iomux.c
@@ -72,6 +72,7 @@
#else /* __rtems__ */
#include <bsp.h>
#include <bsp/fdt.h>
+#include <bsp/imx-iomux.h>
#include <rtems/sysinit.h>
#include <errno.h>
#include <libfdt.h>
@@ -163,6 +164,10 @@ imx_iomux_init(void)
node = fdt_node_offset_by_compatible(fdt, -1,
"fsl,imx6ul-iomuxc");
}
+ if (node < 0) {
+ node = fdt_node_offset_by_compatible(fdt, -1,
+ "nxp,imxrt1050-iomuxc");
+ }
sc = iomux_sc;
sc->regs = imx_get_reg_of_node(fdt, node);
diff --git a/bsps/include/bsp/fatal.h b/bsps/include/bsp/fatal.h
index a66073ae3d..ec5902755e 100644
--- a/bsps/include/bsp/fatal.h
+++ b/bsps/include/bsp/fatal.h
@@ -157,7 +157,22 @@ typedef enum {
RISCV_FATAL_NO_TLCLOCK_FREQUENCY_IN_DEVICE_TREE,
/* GRLIB fatal codes */
- GRLIB_FATAL_CLOCK_NO_IRQMP_TIMESTAMP_SUPPORT = BSP_FATAL_CODE_BLOCK(14)
+ GRLIB_FATAL_CLOCK_NO_IRQMP_TIMESTAMP_SUPPORT = BSP_FATAL_CODE_BLOCK(14),
+
+ /* i.MXRT fatal codes */
+ IMXRT_FATAL_NO_CONSOLE = BSP_FATAL_CODE_BLOCK(15),
+ IMXRT_FATAL_LPUART_INVALID_FDT,
+ IMXRT_FATAL_LPUART_ALLOC_FAILED,
+ IMXRT_FATAL_LPUART_INSTALL_FAILED,
+ IMXRT_FATAL_LPSPI_INVALID_FDT,
+ IMXRT_FATAL_LPSPI_ALLOC_FAILED,
+ IMXRT_FATAL_LPSPI_HW_INIT_FAILED,
+ IMXRT_FATAL_LPSPI_REGISTER_FAILED,
+ IMXRT_FATAL_LPI2C_INVALID_FDT,
+ IMXRT_FATAL_LPI2C_ALLOC_FAILED,
+ IMXRT_FATAL_LPI2C_HW_INIT_FAILED,
+ IMXRT_FATAL_LPI2C_REGISTER_FAILED,
+ IMXRT_FATAL_LPI2C_UNSUPPORTED_HARDWARE,
} bsp_fatal_code;
RTEMS_NO_RETURN static inline void
diff --git a/spec/build/bsps/arm/imxrt/abi.yml b/spec/build/bsps/arm/imxrt/abi.yml
new file mode 100644
index 0000000000..7a95742c36
--- /dev/null
+++ b/spec/build/bsps/arm/imxrt/abi.yml
@@ -0,0 +1,20 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-string: null
+- split: null
+- env-append: null
+build-type: option
+copyrights:
+- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+default:
+- -mthumb
+- -mcpu=cortex-m7
+- -mfpu=fpv5-d16
+- -mfloat-abi=hard
+default-by-variant: []
+description: |
+ ABI flags
+enabled-by: true
+links: []
+name: ABI_FLAGS
+type: build
diff --git a/spec/build/bsps/arm/imxrt/bspimxrt.yml b/spec/build/bsps/arm/imxrt/bspimxrt.yml
new file mode 100644
index 0000000000..7e97a9583c
--- /dev/null
+++ b/spec/build/bsps/arm/imxrt/bspimxrt.yml
@@ -0,0 +1,248 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+arch: arm
+bsp: imxrt1052
+build-type: bsp
+cflags: []
+copyrights:
+- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+cppflags: []
+enabled-by: true
+family: imxrt
+includes:
+ - bsps/arm/shared/include
+install:
+- destination: ${BSP_INCLUDEDIR}
+ source:
+ - bsps/arm/imxrt/include/bsp.h
+ - bsps/arm/imxrt/include/chip.h
+ - bsps/arm/imxrt/include/fsl_adc_etc.h
+ - bsps/arm/imxrt/include/fsl_adc.h
+ - bsps/arm/imxrt/include/fsl_aipstz.h
+ - bsps/arm/imxrt/include/fsl_aoi.h
+ - bsps/arm/imxrt/include/fsl_bee.h
+ - bsps/arm/imxrt/include/fsl_cache.h
+ - bsps/arm/imxrt/include/fsl_clock.h
+ - bsps/arm/imxrt/include/fsl_clock_config.h
+ - bsps/arm/imxrt/include/fsl_cmp.h
+ - bsps/arm/imxrt/include/fsl_common.h
+ - bsps/arm/imxrt/include/fsl_csi.h
+ - bsps/arm/imxrt/include/fsl_dcdc.h
+ - bsps/arm/imxrt/include/fsl_dcp.h
+ - bsps/arm/imxrt/include/fsl_device_registers.h
+ - bsps/arm/imxrt/include/fsl_dmamux.h
+ - bsps/arm/imxrt/include/fsl_edma.h
+ - bsps/arm/imxrt/include/fsl_elcdif.h
+ - bsps/arm/imxrt/include/fsl_enc.h
+ - bsps/arm/imxrt/include/fsl_enet.h
+ - bsps/arm/imxrt/include/fsl_ewm.h
+ - bsps/arm/imxrt/include/fsl_flexcan.h
+ - bsps/arm/imxrt/include/fsl_flexio_camera_edma.h
+ - bsps/arm/imxrt/include/fsl_flexio_camera.h
+ - bsps/arm/imxrt/include/fsl_flexio.h
+ - bsps/arm/imxrt/include/fsl_flexio_i2c_master.h
+ - bsps/arm/imxrt/include/fsl_flexio_i2s_edma.h
+ - bsps/arm/imxrt/include/fsl_flexio_i2s.h
+ - bsps/arm/imxrt/include/fsl_flexio_mculcd_edma.h
+ - bsps/arm/imxrt/include/fsl_flexio_mculcd.h
+ - bsps/arm/imxrt/include/fsl_flexio_spi_edma.h
+ - bsps/arm/imxrt/include/fsl_flexio_spi.h
+ - bsps/arm/imxrt/include/fsl_flexio_uart_edma.h
+ - bsps/arm/imxrt/include/fsl_flexio_uart.h
+ - bsps/arm/imxrt/include/fsl_flexram_allocate.h
+ - bsps/arm/imxrt/include/fsl_flexram.h
+ - bsps/arm/imxrt/include/fsl_flexspi.h
+ - bsps/arm/imxrt/include/fsl_flexspi_nor_boot.h
+ - bsps/arm/imxrt/include/fsl_gpc.h
+ - bsps/arm/imxrt/include/fsl_gpio.h
+ - bsps/arm/imxrt/include/fsl_gpt.h
+ - bsps/arm/imxrt/include/fsl_iomuxc.h
+ - bsps/arm/imxrt/include/fsl_kpp.h
+ - bsps/arm/imxrt/include/fsl_lpi2c_edma.h
+ - bsps/arm/imxrt/include/fsl_lpi2c.h
+ - bsps/arm/imxrt/include/fsl_lpspi_edma.h
+ - bsps/arm/imxrt/include/fsl_lpspi.h
+ - bsps/arm/imxrt/include/fsl_lpuart_edma.h
+ - bsps/arm/imxrt/include/fsl_lpuart.h
+ - bsps/arm/imxrt/include/fsl_ocotp.h
+ - bsps/arm/imxrt/include/fsl_pin_mux.h
+ - bsps/arm/imxrt/include/fsl_pit.h
+ - bsps/arm/imxrt/include/fsl_pmu.h
+ - bsps/arm/imxrt/include/fsl_pwm.h
+ - bsps/arm/imxrt/include/fsl_pxp.h
+ - bsps/arm/imxrt/include/fsl_qtmr.h
+ - bsps/arm/imxrt/include/fsl_rtwdog.h
+ - bsps/arm/imxrt/include/fsl_sai_edma.h
+ - bsps/arm/imxrt/include/fsl_sai.h
+ - bsps/arm/imxrt/include/fsl_semc.h
+ - bsps/arm/imxrt/include/fsl_snvs_hp.h
+ - bsps/arm/imxrt/include/fsl_snvs_lp.h
+ - bsps/arm/imxrt/include/fsl_spdif_edma.h
+ - bsps/arm/imxrt/include/fsl_spdif.h
+ - bsps/arm/imxrt/include/fsl_src.h
+ - bsps/arm/imxrt/include/fsl_tempmon.h
+ - bsps/arm/imxrt/include/fsl_trng.h
+ - bsps/arm/imxrt/include/fsl_tsc.h
+ - bsps/arm/imxrt/include/fsl_usdhc.h
+ - bsps/arm/imxrt/include/fsl_wdog.h
+ - bsps/arm/imxrt/include/fsl_xbara.h
+ - bsps/arm/imxrt/include/fsl_xbarb.h
+ - bsps/arm/imxrt/include/MIMXRT1052_features.h
+ - bsps/arm/imxrt/include/MIMXRT1052.h
+ - bsps/arm/imxrt/include/system_MIMXRT1052.h
+ - bsps/arm/imxrt/include/tm27.h
+- destination: ${BSP_INCLUDEDIR}/arm/freescale/imx
+ source:
+ - bsps/arm/shared/include/arm/freescale/imx/imx_iomuxreg.h
+ - bsps/arm/shared/include/arm/freescale/imx/imx_iomuxvar.h
+- destination: ${BSP_INCLUDEDIR}/bsp
+ source:
+ - bsps/arm/imxrt/include/bsp/irq.h
+ - bsps/arm/imxrt/include/bsp/flash-headers.h
+ - bsps/arm/shared/include/bsp/imx-gpio.h
+ - bsps/arm/shared/include/bsp/imx-iomux.h
+- destination: ${BSP_INCLUDEDIR}/imxrt
+ source:
+ - bsps/arm/imxrt/include/imxrt/memory.h
+ - bsps/arm/imxrt/include/imxrt/imxrt1050-pinfunc.h
+- destination: ${BSP_LIBDIR}
+ source:
+ - bsps/arm/imxrt/start/linkcmds.flexspi
+ - bsps/arm/imxrt/start/linkcmds.sdram
+links:
+- role: build-dependency
+ uid: ../grp
+- role: build-dependency
+ uid: abi
+- role: build-dependency
+ uid: ../../optconsolebaud
+- role: build-dependency
+ uid: ../../optconsoleirq
+- role: build-dependency
+ uid: optlinkcmds
+- role: build-dependency
+ uid: optmemflashcfgsz
+- role: build-dependency
+ uid: optmemflashivtsz
+- role: build-dependency
+ uid: optmemflexspisz
+- role: build-dependency
+ uid: optmemnullsz
+- role: build-dependency
+ uid: optmemsdrambase
+- role: build-dependency
+ uid: optmemsdramsz
+- role: build-dependency
+ uid: optmemsdramnocachesz
+- role: build-dependency
+ uid: ../start
+- role: build-dependency
+ uid: ../../obj
+- role: build-dependency
+ uid: ../../objirq
+- role: build-dependency
+ uid: ../../opto2
+- role: build-dependency
+ uid: linkcmds
+- role: build-dependency
+ uid: linkcmdsmemory
+- role: build-dependency
+ uid: ../../bspopts
+source:
+- bsps/arm/imxrt/console/console.c
+- bsps/arm/imxrt/dts/imxrt1050-evkb.c
+- bsps/arm/imxrt/i2c/imxrt-lpi2c.c
+- bsps/arm/imxrt/nxp/boards/evkbimxrt1050/clock_config.c
+- bsps/arm/imxrt/nxp/boards/evkbimxrt1050/pin_mux.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_adc.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_adc_etc.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_aipstz.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_aoi.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_bee.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_cache.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_clock.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_cmp.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_common.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_csi.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_dcdc.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_dcp.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_dmamux.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_edma.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_elcdif.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_enc.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_enet.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_ewm.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_flexcan.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_flexio.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_flexio_camera.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_flexio_camera_edma.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_flexio_i2c_master.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_flexio_i2s.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_flexio_i2s_edma.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_flexio_mculcd.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_flexio_mculcd_edma.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_flexio_spi.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_flexio_spi_edma.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_flexio_uart.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_flexio_uart_edma.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_flexram_allocate.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_flexram.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_flexspi.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_gpc.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_gpio.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_gpt.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_kpp.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_lpi2c.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_lpi2c_edma.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_lpspi.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_lpspi_edma.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_lpuart.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_lpuart_edma.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_ocotp.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_pit.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_pmu.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_pwm.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_pxp.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_qtmr.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_rtwdog.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_sai.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_sai_edma.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_semc.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_snvs_hp.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_snvs_lp.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_spdif.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_spdif_edma.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_src.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_tempmon.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_trng.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_tsc.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_usdhc.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_wdog.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_xbara.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_xbarb.c
+- bsps/arm/imxrt/nxp/devices/MIMXRT1052/xip/fsl_flexspi_nor_boot.c
+- bsps/arm/imxrt/spi/imxrt-lpspi.c
+- bsps/arm/imxrt/start/bspstart.c
+- bsps/arm/imxrt/start/bspstarthooks.c
+- bsps/arm/imxrt/start/flash-boot-data.c
+- bsps/arm/imxrt/start/flash-config.c
+- bsps/arm/imxrt/start/flash-dcd.c
+- bsps/arm/imxrt/start/flash-ivt.c
+- bsps/arm/imxrt/start/imxrt-ffec-init.c
+- bsps/arm/shared/cache/cache-v7m.c
+- bsps/arm/shared/clock/clock-armv7m.c
+- bsps/arm/shared/cpucounter/cpucounter-armv7m.c
+- bsps/arm/shared/irq/irq-armv7m.c
+- bsps/arm/shared/irq/irq-dispatch-armv7m.c
+- bsps/arm/shared/pins/imx-gpio.c
+- bsps/arm/shared/pins/imx_iomux.c
+- bsps/arm/shared/start/bsp-start-memcpy.S
+- bsps/arm/shared/start/bspreset-armv7m.c
+- bsps/shared/dev/btimer/btimer-stub.c
+- bsps/shared/dev/getentropy/getentropy-cpucounter.c
+- bsps/shared/dev/serial/console-termios.c
+- bsps/shared/irq/irq-default-handler.c
+- bsps/shared/start/bspfatal-default.c
+- bsps/shared/start/bspgetworkarea-default.c
+- bsps/shared/start/sbrk.c
+- bsps/shared/start/stackalloc.c
+type: build
diff --git a/spec/build/bsps/arm/imxrt/linkcmds.yml b/spec/build/bsps/arm/imxrt/linkcmds.yml
new file mode 100644
index 0000000000..3e57b9fd7c
--- /dev/null
+++ b/spec/build/bsps/arm/imxrt/linkcmds.yml
@@ -0,0 +1,11 @@
+build-type: config-file
+content: |
+ INCLUDE ${IMXRT_DEFAULT_LINKCMDS}
+enabled-by: true
+install-path: ${BSP_LIBDIR}
+links: []
+target: linkcmds
+type: build
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+copyrights:
+- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
diff --git a/spec/build/bsps/arm/imxrt/linkcmdsmemory.yml b/spec/build/bsps/arm/imxrt/linkcmdsmemory.yml
new file mode 100644
index 0000000000..86dc37c3bd
--- /dev/null
+++ b/spec/build/bsps/arm/imxrt/linkcmdsmemory.yml
@@ -0,0 +1,67 @@
+build-type: config-file
+content: |
+ MEMORY {
+ NULL : ORIGIN = 0x00000000, LENGTH = ${IMXRT_MEMORY_NULL_SIZE:#010x}
+ ITCM : ORIGIN = ${IMXRT_MEMORY_NULL_SIZE:#010x}, LENGTH = 512k - ${IMXRT_MEMORY_NULL_SIZE:#010x}
+ DTCM : ORIGIN = 0x20000000, LENGTH = 512k
+ OCRAM : ORIGIN = 0x20200000, LENGTH = 512k
+ PERIPHERAL : ORIGIN = 0x40000000, LENGTH = 0x20000000
+ FLEXSPI_CONFIG : ORIGIN = 0x60000000, LENGTH = ${IMXRT_MEMORY_FLASH_CFG_SIZE:#010x}
+ FLEXSPI_IVT : ORIGIN = 0x60000000 + ${IMXRT_MEMORY_FLASH_CFG_SIZE:#010x}, LENGTH = ${IMXRT_MEMORY_FLASH_IVT_SIZE:#010x}
+ FLEXSPI : ORIGIN = 0x60000000 + ${IMXRT_MEMORY_FLASH_CFG_SIZE:#010x} + ${IMXRT_MEMORY_FLASH_IVT_SIZE:#010x}, LENGTH = ${IMXRT_MEMORY_FLEXSPI_FLASH_SIZE:#010x} - ${IMXRT_MEMORY_FLASH_CFG_SIZE:#010x} - ${IMXRT_MEMORY_FLASH_IVT_SIZE:#010x}
+ FLEXSPI_FIFO : ORIGIN = 0x7F800000, LENGTH = 8M
+ SDRAM : ORIGIN = ${IMXRT_MEMORY_SDRAM_BASE:#010x}, LENGTH = ${IMXRT_MEMORY_SDRAM_SIZE:#010x} - ${IMXRT_MEMORY_SDRAM_NOCACHE_SIZE:#010x}
+ SDRAM_NOCACHE : ORIGIN = ${IMXRT_MEMORY_SDRAM_BASE:#010x} + ${IMXRT_MEMORY_SDRAM_SIZE:#010x} - ${IMXRT_MEMORY_SDRAM_NOCACHE_SIZE:#010x}, LENGTH = ${IMXRT_MEMORY_SDRAM_NOCACHE_SIZE:#010x}
+ }
+
+ imxrt_memory_null_begin = ORIGIN (NULL);
+ imxrt_memory_null_end = ORIGIN (NULL) + LENGTH (NULL);
+ imxrt_memory_null_size = LENGTH (NULL);
+
+ imxrt_memory_itcm_begin = ORIGIN (ITCM);
+ imxrt_memory_itcm_end = ORIGIN (ITCM) + LENGTH (ITCM);
+ imxrt_memory_itcm_size = LENGTH (ITCM);
+
+ imxrt_memory_dtcm_begin = ORIGIN (DTCM);
+ imxrt_memory_dtcm_end = ORIGIN (DTCM) + LENGTH (DTCM);
+ imxrt_memory_dtcm_size = LENGTH (DTCM);
+
+ imxrt_memory_ocram_begin = ORIGIN (OCRAM);
+ imxrt_memory_ocram_end = ORIGIN (OCRAM) + LENGTH (OCRAM);
+ imxrt_memory_ocram_size = LENGTH (OCRAM);
+
+ imxrt_memory_peripheral_begin = ORIGIN (PERIPHERAL);
+ imxrt_memory_peripheral_end = ORIGIN (PERIPHERAL) + LENGTH (PERIPHERAL);
+ imxrt_memory_peripheral_size = LENGTH (PERIPHERAL);
+
+ imxrt_memory_flexspi_config_begin = ORIGIN (FLEXSPI_CONFIG);
+ imxrt_memory_flexspi_config_end = ORIGIN (FLEXSPI_CONFIG) + LENGTH (FLEXSPI_CONFIG);
+ imxrt_memory_flexspi_config_size = LENGTH (FLEXSPI_CONFIG);
+
+ imxrt_memory_flexspi_ivt_begin = ORIGIN (FLEXSPI_IVT);
+ imxrt_memory_flexspi_ivt_end = ORIGIN (FLEXSPI_IVT) + LENGTH (FLEXSPI_IVT);
+ imxrt_memory_flexspi_ivt_size = LENGTH (FLEXSPI_IVT);
+
+ imxrt_memory_flexspi_begin = ORIGIN (FLEXSPI);
+ imxrt_memory_flexspi_end = ORIGIN (FLEXSPI) + LENGTH (FLEXSPI);
+ imxrt_memory_flexspi_size = LENGTH (FLEXSPI);
+
+ imxrt_memory_flexspi_fifo_begin = ORIGIN (FLEXSPI_FIFO);
+ imxrt_memory_flexspi_fifo_end = ORIGIN (FLEXSPI_FIFO) + LENGTH (FLEXSPI_FIFO);
+ imxrt_memory_flexspi_fifo_size = LENGTH (FLEXSPI_FIFO);
+
+ imxrt_memory_sdram_begin = ORIGIN (SDRAM);
+ imxrt_memory_sdram_end = ORIGIN (SDRAM) + LENGTH (SDRAM);
+ imxrt_memory_sdram_size = LENGTH (SDRAM);
+
+ imxrt_memory_sdram_nocache_begin = ORIGIN (SDRAM_NOCACHE);
+ imxrt_memory_sdram_nocache_end = ORIGIN (SDRAM_NOCACHE) + LENGTH (SDRAM_NOCACHE);
+ imxrt_memory_sdram_nocache_size = LENGTH (SDRAM_NOCACHE);
+enabled-by: true
+install-path: ${BSP_LIBDIR}
+links: []
+target: linkcmds.memory
+type: build
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+copyrights:
+- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
diff --git a/spec/build/bsps/arm/imxrt/optlinkcmds.yml b/spec/build/bsps/arm/imxrt/optlinkcmds.yml
new file mode 100644
index 0000000000..ba20c3838f
--- /dev/null
+++ b/spec/build/bsps/arm/imxrt/optlinkcmds.yml
@@ -0,0 +1,16 @@
+actions:
+- get-string: null
+- env-assign: null
+build-type: option
+default: linkcmds.flexspi
+default-by-variant: []
+enabled-by: true
+format: '{}'
+links: []
+name: IMXRT_DEFAULT_LINKCMDS
+description: |
+ The default linker command file. Must be linkcmds.sdram or linkcmds.flexspi.
+type: build
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+copyrights:
+- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
diff --git a/spec/build/bsps/arm/imxrt/optmemflashcfgsz.yml b/spec/build/bsps/arm/imxrt/optmemflashcfgsz.yml
new file mode 100644
index 0000000000..cd65a7a442
--- /dev/null
+++ b/spec/build/bsps/arm/imxrt/optmemflashcfgsz.yml
@@ -0,0 +1,19 @@
+actions:
+- get-integer: null
+- env-assign: null
+build-type: option
+default: 0x1000
+default-by-variant: []
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: IMXRT_MEMORY_FLASH_CFG_SIZE
+description: |
+ Size of the flash configuration area at the start of the FlexSPI / SEMC flash
+ in bytes. Either 4 KByte for FlexSPI NOR / SEMC NOR or 1 Kbyte for most other.
+ Take a look at the i.MX RT1050 Processor Reference Manual chapter 9.7 "Program
+ image" for details.
+type: build
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+copyrights:
+- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
diff --git a/spec/build/bsps/arm/imxrt/optmemflashivtsz.yml b/spec/build/bsps/arm/imxrt/optmemflashivtsz.yml
new file mode 100644
index 0000000000..d1d9516951
--- /dev/null
+++ b/spec/build/bsps/arm/imxrt/optmemflashivtsz.yml
@@ -0,0 +1,18 @@
+actions:
+- get-integer: null
+- env-assign: null
+build-type: option
+default: 0x1000
+default-by-variant: []
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: IMXRT_MEMORY_FLASH_IVT_SIZE
+description: |
+ Size of the image vector table, boot data structure, device configuration data
+ and similar program image header information. Take a look at the i.MX RT1050
+ Processor Reference Manual chapter 9.7 "Program image" for details.
+type: build
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+copyrights:
+- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
diff --git a/spec/build/bsps/arm/imxrt/optmemflexspisz.yml b/spec/build/bsps/arm/imxrt/optmemflexspisz.yml
new file mode 100644
index 0000000000..3750c2c683
--- /dev/null
+++ b/spec/build/bsps/arm/imxrt/optmemflexspisz.yml
@@ -0,0 +1,17 @@
+actions:
+- get-integer: null
+- env-assign: null
+- define-unquoted: IMXRT_MEMORY_FLEXSPI_FLASH_SIZE
+build-type: option
+default: 67108864
+default-by-variant: []
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: IMXRT_MEMORY_FLEXSPI_FLASH_SIZE
+description: |
+ Size of the FlexSPI Flash area in bytes.
+type: build
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+copyrights:
+- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
diff --git a/spec/build/bsps/arm/imxrt/optmemnullsz.yml b/spec/build/bsps/arm/imxrt/optmemnullsz.yml
new file mode 100644
index 0000000000..a298f8192f
--- /dev/null
+++ b/spec/build/bsps/arm/imxrt/optmemnullsz.yml
@@ -0,0 +1,17 @@
+actions:
+- get-integer: null
+- env-assign: null
+build-type: option
+default: 0x400
+default-by-variant: []
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: IMXRT_MEMORY_NULL_SIZE
+description: |
+ Size of the NULL pointer protection area in bytes. This memory area reduces
+ the size of the ITCM available to the application.
+type: build
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+copyrights:
+- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
diff --git a/spec/build/bsps/arm/imxrt/optmemsdrambase.yml b/spec/build/bsps/arm/imxrt/optmemsdrambase.yml
new file mode 100644
index 0000000000..567ceab07c
--- /dev/null
+++ b/spec/build/bsps/arm/imxrt/optmemsdrambase.yml
@@ -0,0 +1,16 @@
+actions:
+- get-integer: null
+- env-assign: null
+build-type: option
+default: 0x80000000
+default-by-variant: []
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: IMXRT_MEMORY_SDRAM_BASE
+description: |
+ Base address of the SDRAM.
+type: build
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+copyrights:
+- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
diff --git a/spec/build/bsps/arm/imxrt/optmemsdramnocachesz.yml b/spec/build/bsps/arm/imxrt/optmemsdramnocachesz.yml
new file mode 100644
index 0000000000..113387d039
--- /dev/null
+++ b/spec/build/bsps/arm/imxrt/optmemsdramnocachesz.yml
@@ -0,0 +1,16 @@
+actions:
+- get-integer: null
+- env-assign: null
+build-type: option
+default: 1048576
+default-by-variant: []
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: IMXRT_MEMORY_SDRAM_NOCACHE_SIZE
+description: |
+ Size of the nocache area at the end of the SDRAM in bytes.
+type: build
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+copyrights:
+- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
diff --git a/spec/build/bsps/arm/imxrt/optmemsdramsz.yml b/spec/build/bsps/arm/imxrt/optmemsdramsz.yml
new file mode 100644
index 0000000000..315b5271dc
--- /dev/null
+++ b/spec/build/bsps/arm/imxrt/optmemsdramsz.yml
@@ -0,0 +1,16 @@
+actions:
+- get-integer: null
+- env-assign: null
+build-type: option
+default: 33554432
+default-by-variant: []
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: IMXRT_MEMORY_SDRAM_SIZE
+description: |
+ Size of the SDRAM in bytes.
+type: build
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+copyrights:
+- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
--
2.26.2
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