[PATCH] bsps/aarch64: Remove erroneous cache feature

[Gedare Bloom]

On Fri, Dec 10, 2021 at 10:19 AM Sebastian Huber
<sebastian.huber at embedded-brains.de> wrote:
>
> On 10/12/2021 16:49, Kinsey Moore wrote:
> > The AArch64 cache implementation does not define
> > rtems_cache_disable_data(), but declares that it does via
> > CPU_CACHE_SUPPORT_PROVIDES_DISABLE_DATA. The existing implementation of
> > _CPU_cache_disable_data() is sufficient to enable this functionality
> > without the erroneous cache feature flag.
> >
> > Closes #4569
>
> Thanks, please check it in.
>
> At least for ARMv7 we have an assembler implementation for this function:
>
> bsps/arm/shared/cache/cache-v7ar-disable-data.S
>
Basically the same code should work for aarch64, replacing the access
with SCTLR_EL3
mrs x0, SCTLR_EL1
bic x0, x0, #0x4
msr SCTLR_EL1, x0
isb


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