[PATCH 19/41] bsps/irq: Implement new directives for GICv2/3

[Gedare Bloom]

On Tue, Jul 13, 2021 at 5:47 PM Chris Johns <chrisj at rtems.org> wrote:
>
> On 13/7/21 10:55 pm, Kinsey Moore wrote:
> > On 7/13/2021 00:16, Sebastian Huber wrote:
> >> On 13/07/2021 04:46, Kinsey Moore wrote:
> >>>> index a1ba5e9112..6f5d4015e4 100644
> >>>> --- a/bsps/shared/dev/irq/arm-gicv2.c
> >>>> +++ b/bsps/shared/dev/irq/arm-gicv2.c
> >>>> @@ -1,5 +1,5 @@
> >>>>   /*
> >>>> - * Copyright (c) 2013, 2019 embedded brains GmbH.  All rights reserved.
> >>>> + * Copyright (c) 2013, 2021 embedded brains GmbH.  All rights reserved.
> >>>>    *
> >>>>    *  embedded brains GmbH
> >>>>    *  Dornierstr. 4
> >>>> @@ -69,6 +69,28 @@ rtems_status_code bsp_interrupt_get_attributes(
> >>>>     rtems_interrupt_attributes *attributes
> >>>>   )
> >>>>   {
> >>>> +  attributes->is_maskable = true;
> >>>> +  attributes->maybe_enable = true;
> >>>> +
> >>>> +  if ( vector <= ARM_GIC_IRQ_SGI_LAST ) {
> >>>> +    attributes->always_enabled = true;
> >>>
> >>> As far as I'm aware, SGIs can be enabled or disabled using GICD_ISENABLER0
> >>> just like
> >>>
> >>> PPI or SPI interrupts for both GICv2 and GICv3. Section 3.1.2 of the GICv2
> >>> architecture
> >>>
> >>> spec (IHI0048B) references this, though I have seen implementations where
> >>> certain SGI
> >>>
> >>> and PPI interrupts are hard-wired enabled or disabled and that state can't be
> >>> changed
> >>>
> >>> (which is also covered in this section).
> >>
> >> Ok, on Qemu and the i.MX7D the SGI are always enabled. I would keep the
> >> attributes like this until we have a system which is different.
>
> Should a comment be added that says this?
>
Yes, in case someone else comes along to add support for a system that
is different, it will help to give them some pointers.

> >> I will remove
> >> the check in bsp_interrupt_vector_enable/disable(). So, in the worst case, the
> >> attributes are wrong.
> > I only mention it because I've seen it on ZynqMP hardware. Interrupt enable bits
> > for interrupts 0-24 are locked with 0-7 permanently enabled and 8-24 permanently
> > disabled. I think the QEMU GICv3 driver allows all SGIs to be enabled or
> > disabled. I tried to get more information about whether those bits can be
> > unlocked, but nothing has been forthcoming:
> > https://forums.xilinx.com/t5/Processor-System-Design-and-AXI/Zynq-Ultrascale-MPSoC-SGI-and-PPI-enable/td-p/1212370
>
> I do not know about the GIC but I know with the ARM debug hardware the
> implementers can wrap the IP in different ways and that means something that is
> user controllable may be fixed in other implementation or brought out to
> external pins in another.
>
> Chris
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