[PATCH v3 1/1] bsps/shared: Allow setting baud rate for zynq uart
Jan.Sommer at dlr.de
Jan.Sommer at dlr.de
Fri Mar 5 18:10:11 UTC 2021
Thanks. Pushed to master.
> -----Original Message-----
> From: Gedare Bloom <gedare at rtems.org>
> Sent: Friday, March 5, 2021 6:48 PM
> To: Sommer, Jan <Jan.Sommer at dlr.de>
> Cc: devel at rtems.org
> Subject: Re: [PATCH v3 1/1] bsps/shared: Allow setting baud rate for zynq
> uart
>
> Looks good to me.
>
> On Fri, Mar 5, 2021 at 10:42 AM Jan Sommer <jan.sommer at dlr.de> wrote:
> >
> > ---
> > bsps/shared/dev/serial/zynq-uart.c | 21 ++++++++++++++++-----
> > 1 file changed, 16 insertions(+), 5 deletions(-)
> >
> > diff --git a/bsps/shared/dev/serial/zynq-uart.c
> > b/bsps/shared/dev/serial/zynq-uart.c
> > index 8f17d3ca65..cd0d0e7584 100644
> > --- a/bsps/shared/dev/serial/zynq-uart.c
> > +++ b/bsps/shared/dev/serial/zynq-uart.c
> > @@ -144,14 +144,22 @@ static bool zynq_uart_set_attributes( {
> > zynq_uart_context *ctx = (zynq_uart_context *) context;
> > volatile zynq_uart *regs = ctx->regs;
> > + int32_t baud;
> > uint32_t brgr = 0;
> > uint32_t bauddiv = 0;
> > uint32_t mode = 0;
> > int rc;
> >
> > - rc = zynq_cal_baud_rate(115200, &brgr, &bauddiv, regs->mode);
> > - if (rc != 0)
> > - return rc;
> > + /*
> > + * Determine the baud rate
> > + */
> > + baud = rtems_termios_baud_to_number(term->c_ospeed);
> > +
> > + if (baud > 0) {
> > + rc = zynq_cal_baud_rate(baud, &brgr, &bauddiv, regs->mode);
> > + if (rc != 0)
> > + return rc;
> > + }
> >
> > /*
> > * Configure the mode register
> > @@ -202,8 +210,11 @@ static bool zynq_uart_set_attributes(
> >
> > regs->control &= ~(ZYNQ_UART_CONTROL_RXEN |
> ZYNQ_UART_CONTROL_TXEN);
> > regs->mode = mode;
> > - regs->baud_rate_gen = ZYNQ_UART_BAUD_RATE_GEN_CD(brgr);
> > - regs->baud_rate_div = ZYNQ_UART_BAUD_RATE_DIV_BDIV(bauddiv);
> > + /* Ignore baud rate of B0. There are no modem control lines to
> > + de-assert */ if (baud > 0) {
> > + regs->baud_rate_gen = ZYNQ_UART_BAUD_RATE_GEN_CD(brgr);
> > + regs->baud_rate_div = ZYNQ_UART_BAUD_RATE_DIV_BDIV(bauddiv);
> > + }
> > regs->control |= ZYNQ_UART_CONTROL_RXEN |
> ZYNQ_UART_CONTROL_TXEN;
> >
> > return true;
> > --
> > 2.17.1
> >
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