[PATCH v2 2/3] bsps: Add MicroBlaze FPGA BSP

Alex White alex.white at oarcorp.com
Tue Oct 5 19:23:35 UTC 2021


From: Hesham ALMatary <heshamelmatary at gmail.com>

---
 .../microblaze_fpga/console/console-io.c      |  74 +++++++++
 .../microblaze/microblaze_fpga/include/bsp.h  |  48 ++++++
 .../microblaze/microblaze_fpga/include/tm27.h |  48 ++++++
 .../microblaze/microblaze_fpga/start/start.S  | 109 +++++++++++++
 .../startup/_exception_handler.S              |  38 +++++
 .../startup/_interrupt_handler.S              |  38 +++++
 .../microblaze_fpga/startup/sim-crtinit.S     |  86 +++++++++++
 .../shared/include/linker-symbols.h           | 104 +++++++++++++
 cpukit/score/cpu/microblaze/cpu.c             |  47 +++++-
 .../microblaze/microblaze-context-switch.S    |  89 +++++++++++
 cpukit/score/cpu/microblaze/rtems/asm.h       |   2 +-
 cpukit/score/cpu/microblaze/rtems/score/cpu.h | 145 ++++++++++--------
 .../cpu/microblaze/rtems/score/microblaze.h   |  35 ++++-
 13 files changed, 784 insertions(+), 79 deletions(-)
 create mode 100644 c/src/lib/libbsp/microblaze/microblaze_fpga/console/console-io.c
 create mode 100644 c/src/lib/libbsp/microblaze/microblaze_fpga/include/bsp.h
 create mode 100644 c/src/lib/libbsp/microblaze/microblaze_fpga/include/tm27.h
 create mode 100644 c/src/lib/libbsp/microblaze/microblaze_fpga/start/start.S
 create mode 100644 c/src/lib/libbsp/microblaze/microblaze_fpga/startup/_exception_handler.S
 create mode 100644 c/src/lib/libbsp/microblaze/microblaze_fpga/startup/_interrupt_handler.S
 create mode 100644 c/src/lib/libbsp/microblaze/microblaze_fpga/startup/sim-crtinit.S
 create mode 100644 c/src/lib/libbsp/microblaze/shared/include/linker-symbols.h
 create mode 100644 cpukit/score/cpu/microblaze/microblaze-context-switch.S

diff --git a/c/src/lib/libbsp/microblaze/microblaze_fpga/console/console-io.c b/c/src/lib/libbsp/microblaze/microblaze_fpga/console/console-io.c
new file mode 100644
index 0000000000..47592967ac
--- /dev/null
+++ b/c/src/lib/libbsp/microblaze/microblaze_fpga/console/console-io.c
@@ -0,0 +1,74 @@
+/**
+ * @file
+ *
+ * @ingroup microblaze_uart
+ *
+ * @brief Console Configuration.
+ */
+
+/*
+ *  Copyright (C) 2015 Hesham Almatary
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <rtems/bspIo.h>
+
+#include <libchip/serial.h>
+
+#include <bspopts.h>
+#include <bsp/uart.h>
+
+console_tbl Console_Configuration_Ports [] = {
+    {
+      .sDeviceName = "/dev/ttyS0",
+      .deviceType = SERIAL_CUSTOM,
+      .pDeviceFns = &microblaze_uart_fns,
+      .deviceProbe = NULL,
+      .pDeviceFlow = NULL,
+      .ulCtrlPort1 = UART_BASEADDRESS,
+      .ulCtrlPort2 = 0,
+      .ulClock = 9600,
+      .ulIntVector = 0
+    }
+};
+
+#define PORT_COUNT \
+  (sizeof(Console_Configuration_Ports) \
+    / sizeof(Console_Configuration_Ports [0]))
+
+unsigned long Console_Configuration_Count = PORT_COUNT;
+
+static void output_char(char c)
+{
+  const console_fns *con =
+    Console_Configuration_Ports [Console_Port_Minor].pDeviceFns;
+
+  if (c == '\n') {
+    con->deviceWritePolled((int) Console_Port_Minor, '\r');
+  }
+  con->deviceWritePolled((int) Console_Port_Minor, c);
+}
+
+BSP_output_char_function_type BSP_output_char = output_char;
+
+BSP_polling_getchar_function_type BSP_poll_char = NULL;
diff --git a/c/src/lib/libbsp/microblaze/microblaze_fpga/include/bsp.h b/c/src/lib/libbsp/microblaze/microblaze_fpga/include/bsp.h
new file mode 100644
index 0000000000..cb72835571
--- /dev/null
+++ b/c/src/lib/libbsp/microblaze/microblaze_fpga/include/bsp.h
@@ -0,0 +1,48 @@
+/*
+ *  Copyright (C) 2015 Hesham Almatary
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _BSP_H
+#define _BSP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <bspopts.h>
+
+#include <rtems.h>
+#include <rtems/iosupp.h>
+#include <rtems/console.h>
+#include <rtems/clockdrv.h>
+
+/* support for simulated clock tick */
+Thread clock_driver_sim_idle_body(uintptr_t);
+#define BSP_IDLE_TASK_BODY clock_driver_sim_idle_body
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/c/src/lib/libbsp/microblaze/microblaze_fpga/include/tm27.h b/c/src/lib/libbsp/microblaze/microblaze_fpga/include/tm27.h
new file mode 100644
index 0000000000..393990157f
--- /dev/null
+++ b/c/src/lib/libbsp/microblaze/microblaze_fpga/include/tm27.h
@@ -0,0 +1,48 @@
+/*
+ *  COPYRIGHT (c) 1989-2011.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _RTEMS_TMTEST27
+#error "This is an RTEMS internal file you must not include directly."
+#endif
+
+#ifndef __tm27_h
+#define __tm27_h
+
+/*
+ *  Define the interrupt mechanism for Time Test 27
+ */
+
+#define MUST_WAIT_FOR_INTERRUPT 0
+
+#define Install_tm27_vector( handler ) /* set_vector( (handler), 6, 1 ) */
+
+#define Cause_tm27_intr()  /* XXX */
+
+#define Clear_tm27_intr()  /* XXX */
+
+#define Lower_tm27_intr() /* empty */
+
+#endif
diff --git a/c/src/lib/libbsp/microblaze/microblaze_fpga/start/start.S b/c/src/lib/libbsp/microblaze/microblaze_fpga/start/start.S
new file mode 100644
index 0000000000..9a994c33f8
--- /dev/null
+++ b/c/src/lib/libbsp/microblaze/microblaze_fpga/start/start.S
@@ -0,0 +1,109 @@
+/* Copyright (c) 2001, 2009 Xilinx, Inc.  All rights reserved. 
+   
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are
+   met:
+   
+   1.  Redistributions source code must retain the above copyright notice,
+   this list of conditions and the following disclaimer. 
+   
+   2.  Redistributions in binary form must reproduce the above copyright
+   notice, this list of conditions and the following disclaimer in the
+   documentation and/or other materials provided with the distribution. 
+   
+   3.  Neither the name of Xilinx nor the names of its contributors may be
+   used to endorse or promote products derived from this software without
+   specific prior written permission. 
+   
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS
+   IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+   TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+   PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+   HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+   TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+   PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+   LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+   NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  
+
+        XMD load *.elf error: 
+        MicroBlaze Vector Map for standalone executables
+
+         Address                Vector type                 Label
+         -------                -----------                 ------    
+
+    	# 0x00 #		(-- IMM --)
+	# 0x04 #                Reset                       _start1
+    
+	# 0x08 #		(-- IMM --)
+	# 0x0c #		Software Exception          _exception_handler
+    
+	# 0x10 #		(-- IMM --)
+	# 0x14 #		Hardware Interrupt          _interrupt_handler
+    
+        # 0x18 #                (-- IMM --)
+        # 0x1C #                Breakpoint Exception        (-- Don't Care --)
+    
+        # 0x20 #                (-- IMM --) 
+        # 0x24 #                Hardware Exception          _hw_exception_handler
+
+*/      
+    
+
+	.globl _start
+        .section .vectors.reset, "ax"
+	.align 2
+        .ent _start
+        .type _start, @function
+_start:
+        brai    _start1
+        .end _start
+    
+        .section .vectors.sw_exception, "ax"
+        .align 2
+_vector_sw_exception:       
+        brai    _exception_handler
+
+        .section .vectors.interrupt, "ax"
+        .align 2
+_vector_interrupt:      
+        brai    _interrupt_handler
+
+        .section .vectors.hw_exception, "ax"
+        .align 2
+_vector_hw_exception:       
+        brai    _hw_exception_handler
+
+        .section .text
+        .globl _start1
+        .align 2
+        .ent _start1
+        .type _start1, @function   
+_start1:
+	//la	r13, r0, _SDA_BASE_         /* Set the Small Data Anchors and the stack pointer */
+	//la	r2, r0, _SDA2_BASE_
+	la	r1, r0, bsp_section_stack_begin-16           /* 16 bytes (4 words are needed by crtinit for args and link reg */
+
+	brlid	r15, _crtinit               /* Initialize BSS and run program */
+	nop
+
+        brlid   r15, exit                   /* Call exit with the return value of main */
+        addik   r5, r3, 0                   
+
+        /* Control does not reach here */
+        .end _start1
+    
+
+/* 
+        _exit 
+        Our simple _exit      
+*/    
+        .globl _exit
+        .align 2
+        .ent _exit
+        .type _exit, @function    
+_exit:
+        bri     0
+	.end _exit        
diff --git a/c/src/lib/libbsp/microblaze/microblaze_fpga/startup/_exception_handler.S b/c/src/lib/libbsp/microblaze/microblaze_fpga/startup/_exception_handler.S
new file mode 100644
index 0000000000..2224c924f7
--- /dev/null
+++ b/c/src/lib/libbsp/microblaze/microblaze_fpga/startup/_exception_handler.S
@@ -0,0 +1,38 @@
+/* Copyright (c) 2001, 2009 Xilinx, Inc.  All rights reserved. 
+   
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are
+   met:
+   
+   1.  Redistributions source code must retain the above copyright notice,
+   this list of conditions and the following disclaimer. 
+   
+   2.  Redistributions in binary form must reproduce the above copyright
+   notice, this list of conditions and the following disclaimer in the
+   documentation and/or other materials provided with the distribution. 
+   
+   3.  Neither the name of Xilinx nor the names of its contributors may be
+   used to endorse or promote products derived from this software without
+   specific prior written permission. 
+   
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS
+   IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+   TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+   PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+   HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+   TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+   PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+   LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+   NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  
+*/
+
+	.text
+	.globl _exception_handler    # Exception Handler Label 
+	.align 2
+	
+	_exception_handler:
+	rtsd    r17, 0
+	nop
diff --git a/c/src/lib/libbsp/microblaze/microblaze_fpga/startup/_interrupt_handler.S b/c/src/lib/libbsp/microblaze/microblaze_fpga/startup/_interrupt_handler.S
new file mode 100644
index 0000000000..844c7d01bd
--- /dev/null
+++ b/c/src/lib/libbsp/microblaze/microblaze_fpga/startup/_interrupt_handler.S
@@ -0,0 +1,38 @@
+/* Copyright (c) 2001, 2009 Xilinx, Inc.  All rights reserved. 
+   
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are
+   met:
+   
+   1.  Redistributions source code must retain the above copyright notice,
+   this list of conditions and the following disclaimer. 
+   
+   2.  Redistributions in binary form must reproduce the above copyright
+   notice, this list of conditions and the following disclaimer in the
+   documentation and/or other materials provided with the distribution. 
+   
+   3.  Neither the name of Xilinx nor the names of its contributors may be
+   used to endorse or promote products derived from this software without
+   specific prior written permission. 
+   
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS
+   IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+   TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+   PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+   HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+   TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+   PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+   LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+   NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  
+*/
+
+	.text
+	.globl _interrupt_handler    # Interrupt Handler Label 
+	.align 2
+
+	_interrupt_handler:
+	rtid    r14, 0
+	nop
diff --git a/c/src/lib/libbsp/microblaze/microblaze_fpga/startup/sim-crtinit.S b/c/src/lib/libbsp/microblaze/microblaze_fpga/startup/sim-crtinit.S
new file mode 100644
index 0000000000..6c88272e9e
--- /dev/null
+++ b/c/src/lib/libbsp/microblaze/microblaze_fpga/startup/sim-crtinit.S
@@ -0,0 +1,86 @@
+## Copyright (c) 2015, Hesham Almatary
+## Copyright (c) 2001, 2009 Xilinx, Inc.  All rights reserved. 
+## 
+## Redistribution and use in source and binary forms, with or without
+## modification, are permitted provided that the following conditions are
+## met:
+## 
+## 1.  Redistributions source code must retain the above copyright notice,
+## this list of conditions and the following disclaimer. 
+## 
+## 2.  Redistributions in binary form must reproduce the above copyright
+## notice, this list of conditions and the following disclaimer in the
+## documentation and/or other materials provided with the distribution. 
+## 
+## 3.  Neither the name of Xilinx nor the names of its contributors may be
+## used to endorse or promote products derived from this software without
+## specific prior written permission. 
+## 
+## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS
+## IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+## TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+## PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+## HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+## SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+## TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+## PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+## LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+## NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+## SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+# 
+# 
+# sim-crtinit.s 
+#
+# Default second stage of C run-time initialization that does not peform
+# BSS initialization to zero. Typical use is on a simulator.      
+#    
+
+	.globl _crtinit
+	.align 2
+	.ent _crtinit
+
+_crtinit:
+	addi	r1, r1, -20               	/* Save Link register	 */
+	swi	r15, r1, 0
+
+#ifndef __rtems__
+    	brlid	r15, _program_init              /* Initialize the program  */
+	nop
+
+        brlid   r15, __init                     /* Invoke language initialization functions */
+        nop
+#endif    
+
+
+  /* Init .bss */
+  addi  r6, r0, bsp_section_bss_begin
+  addi  r7, r0, bsp_section_bss_end
+  
+_clear_bss_loop:  
+  swi   r0, r6, 0
+  
+  addi  r6, r6, 4
+  cmpu  r8, r6, r7
+  bgti  r8, _clear_bss_loop
+  
+	addi	r6, r0, 0                       /* Initialize argc = 1 and argv = NULL and envp = NULL  */
+	addi	r7, r0, 0			
+      	brlid	r15, boot_card                  /* Execute the program */
+	addi	r5, r0, 0			
+
+        addik   r19, r3, 0                      /* Save return value */
+    
+#ifndef __rtems__
+        brlid   r15, __fini                     /* Invoke language cleanup functions */
+        nop
+
+	brlid	r15, _program_clean             /* Cleanup the program  */
+	nop
+#endif
+
+	lw	r15, r1, r0                     /* Return back to CRT   */
+        addik   r3, r19, 0                      /* Restore return value */
+	rtsd	r15, 8
+    	addi	r1, r1, 20
+	.end _crtinit
+
diff --git a/c/src/lib/libbsp/microblaze/shared/include/linker-symbols.h b/c/src/lib/libbsp/microblaze/shared/include/linker-symbols.h
new file mode 100644
index 0000000000..60a5057486
--- /dev/null
+++ b/c/src/lib/libbsp/microblaze/shared/include/linker-symbols.h
@@ -0,0 +1,104 @@
+/*
+ *  Copyright (C) 2015 Hesham Almatary
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_MICROBLAZE_SHARED_LINKER_SYMBOLS_H
+#define LIBBSP_MICROBLAZE_SHARED_LINKER_SYMBOLS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/**
+ * @defgroup microblaze Linker Support
+ *
+ * @ingroup microblaze_shared
+ *
+ * @brief Linker support.
+ *
+ * @{
+ */
+
+#ifndef ASM
+  #define LINKER_SYMBOL(sym) extern char sym [];
+#else
+  #define LINKER_SYMBOL(sym) .extern sym
+#endif
+
+LINKER_SYMBOL(bsp_section_start_begin)
+LINKER_SYMBOL(bsp_section_start_end)
+LINKER_SYMBOL(bsp_section_start_size)
+
+LINKER_SYMBOL(bsp_section_vector_begin)
+LINKER_SYMBOL(bsp_section_vector_end)
+LINKER_SYMBOL(bsp_section_vector_size)
+
+LINKER_SYMBOL(bsp_section_text_begin)
+LINKER_SYMBOL(bsp_section_text_end)
+LINKER_SYMBOL(bsp_section_text_size)
+LINKER_SYMBOL(bsp_section_text_load_begin)
+LINKER_SYMBOL(bsp_section_text_load_end)
+
+LINKER_SYMBOL(bsp_section_rodata_begin)
+LINKER_SYMBOL(bsp_section_rodata_end)
+LINKER_SYMBOL(bsp_section_rodata_size)
+LINKER_SYMBOL(bsp_section_rodata_load_begin)
+LINKER_SYMBOL(bsp_section_rodata_load_end)
+
+LINKER_SYMBOL(bsp_section_data_begin)
+LINKER_SYMBOL(bsp_section_data_end)
+LINKER_SYMBOL(bsp_section_data_size)
+LINKER_SYMBOL(bsp_section_data_load_begin)
+LINKER_SYMBOL(bsp_section_data_load_end)
+
+LINKER_SYMBOL(bsp_section_bss_begin)
+LINKER_SYMBOL(bsp_section_bss_end)
+LINKER_SYMBOL(bsp_section_bss_size)
+
+LINKER_SYMBOL(bsp_section_work_begin)
+LINKER_SYMBOL(bsp_section_work_end)
+LINKER_SYMBOL(bsp_section_work_size)
+
+LINKER_SYMBOL(bsp_section_stack_begin)
+LINKER_SYMBOL(bsp_section_stack_end)
+LINKER_SYMBOL(bsp_section_stack_size)
+
+LINKER_SYMBOL(bsp_vector_table_begin)
+LINKER_SYMBOL(bsp_vector_table_end)
+LINKER_SYMBOL(bsp_vector_table_size)
+
+LINKER_SYMBOL(bsp_start_vector_table_begin)
+LINKER_SYMBOL(bsp_start_vector_table_end)
+LINKER_SYMBOL(bsp_start_vector_table_size)
+
+LINKER_SYMBOL(bsp_translation_table_base)
+LINKER_SYMBOL(bsp_translation_table_end)
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_MICROBLAZE_SHARED_LINKER_SYMBOLS_H */
diff --git a/cpukit/score/cpu/microblaze/cpu.c b/cpukit/score/cpu/microblaze/cpu.c
index 27dd69b9fb..ca4a3ec2f6 100644
--- a/cpukit/score/cpu/microblaze/cpu.c
+++ b/cpukit/score/cpu/microblaze/cpu.c
@@ -1,14 +1,28 @@
 /*
- *  MicroBlaze CPU Dependent Source
- *
+ *  Copyright (c) 2015, Hesham Almatary
  *  COPYRIGHT (c) 1989-2011.
  *  On-Line Applications Research Corporation (OAR).
  *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.com/license/LICENSE.
- *
- *  $Id: cpu.c,v 1.24 2010/03/27 15:02:26 joel Exp $
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
  */
 
 #ifdef HAVE_CONFIG_H
@@ -42,6 +56,25 @@ void _CPU_Initialize(void)
   /* FP context initialization support goes here */
 }
 
+void _CPU_Context_Initialize(
+  Context_Control *context,
+  void *stack_area_begin,
+  size_t stack_area_size,
+  uint32_t new_level,
+  void (*entry_point)( void ),
+  bool is_fp,
+  void *tls_area
+)
+{
+  uint32_t stack = ((uint32_t) stack_area_begin);
+  uint32_t stack_high = stack + stack_area_size;
+
+  memset(context, 0, sizeof(*context));
+
+  context->r[0] = stack_high;
+  context->r[3] = (uint32_t) entry_point;
+}
+
 /*PAGE
  *
  *  _CPU_ISR_Get_level
diff --git a/cpukit/score/cpu/microblaze/microblaze-context-switch.S b/cpukit/score/cpu/microblaze/microblaze-context-switch.S
new file mode 100644
index 0000000000..c033fb1f5e
--- /dev/null
+++ b/cpukit/score/cpu/microblaze/microblaze-context-switch.S
@@ -0,0 +1,89 @@
+/*
+ *  Copyright (c) 2015, Hesham Almatary
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifdef HAVE_CONFIG_H
+  #include "config.h"
+#endif
+
+#include <rtems/asm.h>
+
+.text
+.align 4
+
+PUBLIC(_CPU_Context_switch)
+PUBLIC(_CPU_Context_restore)
+PUBLIC(_CPU_Context_restore_fp)
+PUBLIC(_CPU_Context_save_fp)
+
+SYM(_CPU_Context_switch):
+    swi     r1,  r5, 0
+    swi     r13, r5, 4
+    swi     r14, r5, 8
+    swi     r15, r5, 12    
+    swi     r16, r5, 16
+    swi     r17, r5, 20
+    swi     r18, r5, 24    
+    swi     r19, r5, 28
+    swi     r20, r5, 32
+    swi     r21, r5, 36
+    swi     r22, r5, 40
+    swi     r23, r5, 44
+    swi     r24, r5, 48
+    swi     r25, r5, 52
+    swi     r26, r5, 56
+    swi     r27, r5, 60    
+    swi     r28, r5, 64    
+    swi     r29, r5, 68    
+    swi     r30, r5, 72
+    swi     r31, r5, 76
+ 
+SYM(restore):   
+    lwi     r1,  r6, 0
+    lwi     r13, r6, 4
+    lwi     r14, r6, 8
+    lwi     r15, r6, 12    
+    lwi     r16, r6, 16
+    lwi     r17, r6, 20
+    lwi     r18, r6, 24    
+    lwi     r19, r6, 28
+    lwi     r20, r6, 32
+    lwi     r21, r6, 36
+    lwi     r22, r6, 40
+    lwi     r23, r6, 44
+    lwi     r24, r6, 48
+    lwi     r25, r6, 52
+    lwi     r26, r6, 56
+    lwi     r27, r6, 60    
+    lwi     r28, r6, 64    
+    lwi     r29, r6, 68    
+    lwi     r30, r6, 72
+    lwi     r31, r6, 76    
+
+    rtsd    r15, 8
+    
+SYM(_CPU_Context_restore):
+    add   r6, r5, r0
+    brai  restore
+
diff --git a/cpukit/score/cpu/microblaze/rtems/asm.h b/cpukit/score/cpu/microblaze/rtems/asm.h
index 13609d2d70..b5a8702f02 100644
--- a/cpukit/score/cpu/microblaze/rtems/asm.h
+++ b/cpukit/score/cpu/microblaze/rtems/asm.h
@@ -19,6 +19,7 @@
  *  notice.  This file is freely distributable as long as the source
  *  of the file is noted.  This file is:
  *
+ *  Copyright (c) 2015, Hesham Almatary
  *  COPYRIGHT (c) 1994-2006.
  *  On-Line Applications Research Corporation (OAR).
  *
@@ -36,7 +37,6 @@
 #define ASM
 #endif
 #include <rtems/score/cpuopts.h>
-#include <rtems/score/no_cpu.h>
 
 #ifndef __USER_LABEL_PREFIX__
 /**
diff --git a/cpukit/score/cpu/microblaze/rtems/score/cpu.h b/cpukit/score/cpu/microblaze/rtems/score/cpu.h
index 4947045c2c..d9f9e8add5 100644
--- a/cpukit/score/cpu/microblaze/rtems/score/cpu.h
+++ b/cpukit/score/cpu/microblaze/rtems/score/cpu.h
@@ -1,3 +1,30 @@
+/*
+ *  Copyright (c) 2015, Hesham Almatary
+ *  COPYRIGHT (c) 1989-2008.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
 /**
  * @file rtems/score/cpu.h
  */
@@ -19,17 +46,6 @@
  *    add CPU family specific information in this section
  */
 
-/*
- *  COPYRIGHT (c) 1989-2008.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.com/license/LICENSE.
- *
- *  $Id: cpu.h,v 1.35 2010/10/21 22:14:20 joel Exp $
- */
-
 #ifndef _RTEMS_SCORE_CPU_H
 #define _RTEMS_SCORE_CPU_H
 
@@ -464,19 +480,7 @@ extern "C" {
  *  to another.
  */
 typedef struct {
-    /** This field is a hint that a port will have a number of integer
-     *  registers that need to be saved at a context switch.
-     */
-    uint32_t   some_integer_register;
-    /** This field is a hint that a port will have a number of system
-     *  registers that need to be saved at a context switch.
-     */
-    uint32_t   some_system_register;
-
-    /** This field is a hint that a port will have a register that
-     *  is the stack pointer.
-     */
-    uint32_t   stack_pointer;
+    uint32_t r[32];
 } Context_Control;
 
 /**
@@ -489,7 +493,7 @@ typedef struct {
  *  @return This method returns the stack pointer.
  */
 #define _CPU_Context_Get_SP( _context ) \
-  (_context)->stack_pointer
+  (_context)->r[0]
 
 /**
  *  @ingroup CPUContext Management
@@ -799,43 +803,32 @@ uint32_t   _CPU_ISR_Get_level( void );
 
 /* end of ISR handler macros */
 
-/* Context handler macros */
-
 /**
- *  @ingroup CPUContext
- *  Initialize the context to a state suitable for starting a
- *  task after a context restore operation.  Generally, this
- *  involves:
- *
- *     - setting a starting address
- *     - preparing the stack
- *     - preparing the stack and frame pointers
- *     - setting the proper interrupt level in the context
- *     - initializing the floating point context
- *
- *  This routine generally does not set any unnecessary register
- *  in the context.  The state of the "general data" registers is
- *  undefined at task start time.
- *
- *  @param[in] _the_context is the context structure to be initialized
- *  @param[in] _stack_base is the lowest physical address of this task's stack
- *  @param[in] _size is the size of this task's stack
- *  @param[in] _isr is the interrupt disable level
- *  @param[in] _entry_point is the thread's entry point.  This is
- *         always @a _Thread_Handler
- *  @param[in] _is_fp is TRUE if the thread is to be a floating
- *        point thread.  This is typically only used on CPUs where the
- *        FPU may be easily disabled by software such as on the SPARC
- *        where the PSR contains an enable FPU bit.
- *
- *  Port Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
-                                 _isr, _entry_point, _is_fp ) \
-  { \
-  }
+ * @brief Initializes the CPU context.
+ *
+ * The following steps are performed:
+ *  - setting a starting address
+ *  - preparing the stack
+ *  - preparing the stack and frame pointers
+ *  - setting the proper interrupt level in the context
+ *
+ * @param[in] context points to the context area
+ * @param[in] stack_area_begin is the low address of the allocated stack area
+ * @param[in] stack_area_size is the size of the stack area in bytes
+ * @param[in] new_level is the interrupt level for the task
+ * @param[in] entry_point is the task's entry point
+ * @param[in] is_fp is set to @c true if the task is a floating point task
+ * @param[in] tls_area is the thread-local storage (TLS) area
+ */
+void _CPU_Context_Initialize(
+  Context_Control *context,
+  void *stack_area_begin,
+  size_t stack_area_size,
+  uint32_t new_level,
+  void (*entry_point)( void ),
+  bool is_fp,
+  void *tls_area
+);
 
 /**
  *  This routine is responsible for somehow restarting the currently
@@ -916,9 +909,9 @@ uint32_t   _CPU_ISR_Get_level( void );
  *
  *  XXX document implementation including references if appropriate
  */
-#define _CPU_Fatal_halt( _error ) \
-  { \
-  }
+#define _CPU_Fatal_halt(_source, _error ) \
+        printk("Fatal Error %d.%d Halted\n",_source, _error); \
+        for(;;)
 
 /* end of Fatal Error manager macros */
 
@@ -1059,6 +1052,21 @@ uint32_t   _CPU_ISR_Get_level( void );
 
 #endif
 
+#define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC FALSE
+#define CPU_TIMESTAMP_USE_INT64 TRUE
+#define CPU_TIMESTAMP_USE_INT64_INLINE FALSE
+
+typedef struct {
+/* There is no CPU specific per-CPU state */
+} CPU_Per_CPU_control;
+
+#define CPU_SIZEOF_POINTER 4
+#define CPU_PER_CPU_CONTROL_SIZE 0
+
+typedef struct {
+  uint32_t r[32];
+} CPU_Exception_frame;
+
 /* end of Priority handler macros */
 
 /* functions */
@@ -1256,6 +1264,15 @@ static inline uint32_t CPU_swap_u32(
 #define CPU_swap_u16( value ) \
   (((value&0xff) << 8) | ((value >> 8)&0xff))
 
+typedef uint32_t CPU_Counter_ticks;
+
+CPU_Counter_ticks _CPU_Counter_read( void );
+
+CPU_Counter_ticks _CPU_Counter_difference(
+  CPU_Counter_ticks second,
+  CPU_Counter_ticks first
+);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/cpukit/score/cpu/microblaze/rtems/score/microblaze.h b/cpukit/score/cpu/microblaze/rtems/score/microblaze.h
index 06f79aadea..df521f1bd7 100644
--- a/cpukit/score/cpu/microblaze/rtems/score/microblaze.h
+++ b/cpukit/score/cpu/microblaze/rtems/score/microblaze.h
@@ -1,20 +1,41 @@
+/*
+ *  Copyright (c) 2015, Hesham Almatary
+ *  COPYRIGHT (c) 1989-2008.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
 /*  
  *  This file sets up basic CPU dependency settings based on
  *  compiler settings.  For example, it can determine if
  *  floating point is available.  This particular implementation
  *  is specified to the NO CPU port.
  *
- *  COPYRIGHT (c) 1989-2011.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.com/license/LICENSE.
- *
  *  $Id: no_cpu.h,v 1.9 2009/12/02 09:48:25 ralf Exp $
  *
  */
 
+
 #ifndef _RTEMS_SCORE_NO_CPU_H
 #define _RTEMS_SCORE_NO_CPU_H
 
-- 
2.27.0



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