[PATCH v6 06/10] bsps/arm/stm32f4: Make bspstart use HAL
Duc Doan
dtbpkmte at gmail.com
Sun Aug 7 10:58:18 UTC 2022
This patch changes bspstart to use HAL for clock and sysyem
initialization.
---
bsps/arm/stm32f4/start/bspstart.c | 199 ++++++++++++++++++++++++++++--
1 file changed, 186 insertions(+), 13 deletions(-)
diff --git a/bsps/arm/stm32f4/start/bspstart.c b/bsps/arm/stm32f4/start/bspstart.c
index 0ec5ac27b5..2297430844 100644
--- a/bsps/arm/stm32f4/start/bspstart.c
+++ b/bsps/arm/stm32f4/start/bspstart.c
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2012 Sebastian Huber. All rights reserved.
+ * Copyright (c) 2022 Duc Doan (dtbpkmte at gmail.com).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
@@ -7,15 +8,23 @@
*/
#include <bsp.h>
+#include <bspopts.h>
#include <bsp/io.h>
#include <bsp/irq.h>
#include <bsp/bootcard.h>
#include <bsp/irq-generic.h>
#include <assert.h>
+#ifndef __rtems__
#include <bsp/stm32f4.h>
+#endif /* __rtems__ */
+#ifdef __rtems__
+#include <stm32f4xx.h>
+#include <bsp/gpio2.h>
+#endif /* __rtems__ */
#ifdef STM32F4_FAMILY_F4XXXX
+#ifndef __rtems__
#include <bsp/stm32f4xxxx_rcc.h>
#include <bsp/stm32f4xxxx_flash.h>
@@ -24,28 +33,191 @@ static rtems_status_code set_system_clk(
uint32_t hse_clk,
uint32_t hse_flag
);
+#endif /* __rtems__ */
+
+#ifdef __rtems__
+/* Get number of milliseconds elapsed since startup */
+uint32_t HAL_GetTick(void)
+{
+ return rtems_clock_get_ticks_since_boot() *
+ rtems_configuration_get_milliseconds_per_tick();
+}
+
+/**
+ * @brief This function is executed in case of error occurrence.
+ * @retval None
+ */
+static void Error_Handler(void)
+{
+ /* USER CODE BEGIN Error_Handler_Debug */
+ /* User can add his own implementation to report the HAL error return state */
+ __disable_irq();
+ while (1)
+ {
+ }
+ /* USER CODE END Error_Handler_Debug */
+}
+
+static rtems_status_code SystemClock_Config(void)
+{
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+ uint32_t use_hse = STM32F4_USE_HSE, sys_clk = STM32F4_SYSCLK / 1000000L, hse_clk = STM32F4_HSE_FREQUENCY / 1000000L, src_clk;
+ uint32_t sys_clk_src;
+ uint32_t flash_latency = FLASH_LATENCY_0;
+ uint32_t pll_m = 0, pll_n = 0, pll_p = 0, pll_q = 0;
+ uint32_t apbpre1 = 0, apbpre2 = 0;
+
+ if (sys_clk == 16 && hse_clk != 16) {
+ sys_clk_src = RCC_SYSCLKSOURCE_HSI;
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ flash_latency = FLASH_LATENCY_0;
+ } else if (sys_clk == hse_clk) {
+ sys_clk_src = RCC_SYSCLKSOURCE_HSE;
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+ flash_latency = FLASH_LATENCY_0;
+ } else {
+ sys_clk_src = RCC_SYSCLKSOURCE_PLLCLK;
+ if (sys_clk > 180) {
+ return RTEMS_INVALID_NUMBER;
+ } else if (sys_clk >= 96) {
+ pll_n = sys_clk << 1;
+ pll_p = RCC_PLLP_DIV2;
+ } else if (sys_clk >= 48) {
+ pll_n = sys_clk << 2;
+ pll_p = RCC_PLLP_DIV4;
+ } else if (sys_clk >= 24) {
+ pll_n = sys_clk << 3;
+ pll_p = RCC_PLLP_DIV8;
+ } else {
+ return RTEMS_INVALID_NUMBER;
+ }
+
+ if (hse_clk == 0 || use_hse == 0) {
+ src_clk = 16;
+ use_hse = 0;
+ } else {
+ src_clk = hse_clk;
+ }
+
+ pll_m = src_clk;
+
+ pll_q = ((long) (src_clk * pll_n)) / pll_m / 48;
+ if (pll_q < 2) {
+ pll_q = 2;
+ }
+
+ /* APB1 prescaler, APB1 clock must be < 42MHz */
+ apbpre1 = (sys_clk * 100) / 42;
+
+ if ( apbpre1 <= 100 ) {
+ apbpre1 = RCC_HCLK_DIV1;
+ } else if (apbpre1 <= 200) {
+ apbpre1 = RCC_HCLK_DIV2;
+ } else if (apbpre1 <= 400) {
+ apbpre1 = RCC_HCLK_DIV4;
+ } else if (apbpre1 <= 800) {
+ apbpre1 = RCC_HCLK_DIV8;
+ } else if (apbpre1) {
+ apbpre1 = RCC_HCLK_DIV16;
+ }
+
+ /* APB2 prescaler, APB2 clock must be < 84MHz */
+ apbpre2 = (sys_clk * 100) / 84;
+
+ if (apbpre2 <= 100) {
+ apbpre2 = RCC_HCLK_DIV1;
+ } else if (apbpre2 <= 200) {
+ apbpre2 = RCC_HCLK_DIV2;
+ } else if (apbpre2 <= 400) {
+ apbpre2 = RCC_HCLK_DIV4;
+ } else if (apbpre2 <= 800) {
+ apbpre2 = RCC_HCLK_DIV8;
+ } else {
+ apbpre2 = RCC_HCLK_DIV16;
+ }
+
+ if (use_hse) {
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ } else {
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ }
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLM = pll_m;
+ RCC_OscInitStruct.PLL.PLLN = pll_n;
+ RCC_OscInitStruct.PLL.PLLP = pll_p;
+ RCC_OscInitStruct.PLL.PLLQ = pll_q;
+ flash_latency = FLASH_LATENCY_5;
+ }
+
+ HAL_StatusTypeDef status = HAL_RCC_OscConfig(&RCC_OscInitStruct);
+ if (status != HAL_OK)
+ {
+ return RTEMS_UNSATISFIED;
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+ |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = sys_clk_src;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = apbpre1;
+ RCC_ClkInitStruct.APB2CLKDivider = apbpre2;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, flash_latency) != HAL_OK)
+ {
+ return RTEMS_UNSATISFIED;
+ }
+
+ return RTEMS_SUCCESSFUL;
+}
+#endif /* __rtems__ */
static void init_main_osc( void )
{
- volatile stm32f4_rcc *rcc = STM32F4_RCC;
- rtems_status_code status;
+#ifndef __rtems__
+ volatile stm32f4_rcc *rcc = STM32F4_RCC;
+ rtems_status_code status;
- /* Revert to reset values */
- rcc->cr |= RCC_CR_HSION; /* turn on HSI */
+ /* Revert to reset values */
+ rcc->cr |= RCC_CR_HSION; /* turn on HSI */
- while ( !( rcc->cr & RCC_CR_HSIRDY ) ) ;
+ while ( !( rcc->cr & RCC_CR_HSIRDY ) ) ;
- rcc->cfgr &= 0x00000300; /* all prescalers to 0, clock source to HSI */
+ rcc->cfgr &= 0x00000300; /* all prescalers to 0, clock source to HSI */
- rcc->cr &= 0xF0F0FFFD; /* turn off all clocks and PLL except HSI */
+ rcc->cr &= 0xF0F0FFFD; /* turn off all clocks and PLL except HSI */
- status = set_system_clk( STM32F4_SYSCLK / 1000000L,
+ status = set_system_clk( STM32F4_SYSCLK / 1000000L,
STM32F4_HSE_OSCILLATOR / 1000000L,
1 );
- assert( rtems_is_status_successful( status ) );
+ assert( rtems_is_status_successful( status ) );
+#endif /* __rtems__ */
+#ifdef __rtems__
+ HAL_Init();
+ rtems_status_code status = SystemClock_Config();
+ if (status != RTEMS_SUCCESSFUL) {
+ Error_Handler();
+ }
+#endif /* __rtems__ */
}
-
+#ifndef __rtems__
/**
* @brief Sets up clocks configuration.
*
@@ -275,6 +447,7 @@ static rtems_status_code set_system_clk(
return RTEMS_SUCCESSFUL;
}
+#endif /* __rtems__ */
#endif /* STM32F4_FAMILY_F4XXXX */
@@ -289,9 +462,9 @@ static void init_main_osc( void )
void bsp_start( void )
{
- init_main_osc();
+ init_main_osc();
- stm32f4_gpio_set_config_array( &stm32f4_start_config_gpio[ 0 ] );
+ stm32f4_gpio_set_config_array( &stm32f4_start_config_gpio[ 0 ] );
- bsp_interrupt_initialize();
+ bsp_interrupt_initialize();
}
--
2.37.1
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