[PATCH v3] irq/arm-gicv3.h: Customize CPU Interface init

Chris Johns chrisj at rtems.org
Tue Jul 12 06:25:11 UTC 2022

On 11/7/2022 7:16 pm, Sebastian Huber wrote:
> Use the existing WRITE_SR() abstraction to access the interrupt group 0 and 1
> enable registers.  This fixes the build for the AArch32 target.
> Add BSP options which define the initial values of CPU Interface registers.
> ---
> v3:
> * Fix variant-specific default values.
> * Add BSP options for ICC_BPR0, ICC_BPR1, ICC_CTRL, ICC_PMR, and ICC_SRE.

Looks good and tested on Versal hardware.


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