[PATCH v2] aarch64: Use page table level 0

[Sebastian Huber]

On 20.07.22 15:43, Kinsey Moore wrote:
> This alters the AArch64 page table generation and mapping code and MMU
> configuration to use page table level 0 in addition to levels 1, 2, and
> 3. This allows the mapping of up to 48 bits of memory space and is the
> maximum that can be mapped without relying on additional processor
> extensions. Mappings are restricted based on the number of physical
> address bits that the CPU supports.

Looks good.

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