[PATCH 8/8] bsp/stm32h7: remove system files from start directory
Karel Gardas
karel at functional.vision
Sun May 15 20:10:44 UTC 2022
The files are already presented in boards directories and are not needed
in start directory anymore.
Sponsored-By: Precidata
---
bsps/arm/stm32h7/start/stm32h7-config-clk.c | 45 ---
bsps/arm/stm32h7/start/stm32h7-config-osc.c | 52 ---
bsps/arm/stm32h7/start/stm32h7-config-per.c | 62 ---
bsps/arm/stm32h7/start/system_stm32h7xx.c | 416 --------------------
4 files changed, 575 deletions(-)
delete mode 100644 bsps/arm/stm32h7/start/stm32h7-config-clk.c
delete mode 100644 bsps/arm/stm32h7/start/stm32h7-config-osc.c
delete mode 100644 bsps/arm/stm32h7/start/stm32h7-config-per.c
delete mode 100644 bsps/arm/stm32h7/start/system_stm32h7xx.c
diff --git a/bsps/arm/stm32h7/start/stm32h7-config-clk.c b/bsps/arm/stm32h7/start/stm32h7-config-clk.c
deleted file mode 100644
index 3e7c930201..0000000000
--- a/bsps/arm/stm32h7/start/stm32h7-config-clk.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/* SPDX-License-Identifier: BSD-2-Clause */
-
-/*
- * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include <stm32h7/hal.h>
-
-const RCC_ClkInitTypeDef stm32h7_config_clocks = {
- .ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
- | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2
- | RCC_CLOCKTYPE_D3PCLK1 | RCC_CLOCKTYPE_D1PCLK1,
- .SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK,
- .SYSCLKDivider = RCC_SYSCLK_DIV1,
- .AHBCLKDivider = RCC_HCLK_DIV2,
- .APB3CLKDivider = RCC_APB3_DIV2,
- .APB1CLKDivider = RCC_APB1_DIV2,
- .APB2CLKDivider = RCC_APB2_DIV2,
- .APB4CLKDivider = RCC_APB4_DIV2
-};
diff --git a/bsps/arm/stm32h7/start/stm32h7-config-osc.c b/bsps/arm/stm32h7/start/stm32h7-config-osc.c
deleted file mode 100644
index b639c7ca36..0000000000
--- a/bsps/arm/stm32h7/start/stm32h7-config-osc.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/* SPDX-License-Identifier: BSD-2-Clause */
-
-/*
- * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include <stm32h7/hal.h>
-
-const RCC_OscInitTypeDef stm32h7_config_oscillator = {
- .OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE
- | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_HSI48,
- .HSEState = RCC_HSE_ON,
- .LSEState = RCC_LSE_ON,
- .HSIState = RCC_HSI_DIV1,
- .HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT,
- .HSI48State = RCC_HSI48_ON,
- .PLL.PLLState = RCC_PLL_ON,
- .PLL.PLLSource = RCC_PLLSOURCE_HSE,
- .PLL.PLLM = 5,
- .PLL.PLLN = 192,
- .PLL.PLLP = 2,
- .PLL.PLLQ = 12,
- .PLL.PLLR = 2,
- .PLL.PLLRGE = RCC_PLL1VCIRANGE_2,
- .PLL.PLLVCOSEL = RCC_PLL1VCOWIDE,
- .PLL.PLLFRACN = 0
-};
diff --git a/bsps/arm/stm32h7/start/stm32h7-config-per.c b/bsps/arm/stm32h7/start/stm32h7-config-per.c
deleted file mode 100644
index 79aa1494dd..0000000000
--- a/bsps/arm/stm32h7/start/stm32h7-config-per.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/* SPDX-License-Identifier: BSD-2-Clause */
-
-/*
- * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include <stm32h7/hal.h>
-
-const RCC_PeriphCLKInitTypeDef stm32h7_config_peripheral_clocks = {
- .PeriphClockSelection = RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USART3
- | RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1
- | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_FMC | RCC_PERIPHCLK_RNG,
- .PLL2.PLL2M = 3,
- .PLL2.PLL2N = 48,
- .PLL2.PLL2P = 1,
- .PLL2.PLL2Q = 2,
- .PLL2.PLL2R = 2,
- .PLL2.PLL2RGE = RCC_PLL2VCIRANGE_3,
- .PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE,
- .PLL2.PLL2FRACN = 0,
- .PLL3.PLL3M = 25,
- .PLL3.PLL3N = 192,
- .PLL3.PLL3P = 2,
- .PLL3.PLL3Q = 4,
- .PLL3.PLL3R = 2,
- .PLL3.PLL3RGE = RCC_PLL3VCIRANGE_0,
- .PLL3.PLL3VCOSEL = RCC_PLL3VCOWIDE,
- .PLL3.PLL3FRACN = 0,
- .FmcClockSelection = RCC_FMCCLKSOURCE_PLL2,
- .FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL,
- .Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1,
- .Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2,
- .I2c123ClockSelection = RCC_I2C123CLKSOURCE_D2PCLK1,
- .UsbClockSelection = RCC_USBCLKSOURCE_PLL3,
- .RTCClockSelection = RCC_RTCCLKSOURCE_LSE,
- .RngClockSelection = RCC_RNGCLKSOURCE_HSI48
-};
diff --git a/bsps/arm/stm32h7/start/system_stm32h7xx.c b/bsps/arm/stm32h7/start/system_stm32h7xx.c
deleted file mode 100644
index a8a9ff0b4b..0000000000
--- a/bsps/arm/stm32h7/start/system_stm32h7xx.c
+++ /dev/null
@@ -1,416 +0,0 @@
-/**
- ******************************************************************************
- * @file system_stm32h7xx.c
- * @author MCD Application Team
- * @brief CMSIS Cortex-Mx Device Peripheral Access Layer System Source File.
- *
- * This file provides two functions and one global variable to be called from
- * user application:
- * - SystemInit(): This function is called at startup just after reset and
- * before branch to main program. This call is made inside
- * the "startup_stm32h7xx.s" file.
- *
- * - SystemCoreClock variable: Contains the core clock, it can be used
- * by the user application to setup the SysTick
- * timer or configure other parameters.
- *
- * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
- * be called whenever the core clock is changed
- * during program execution.
- *
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32h7xx_system
- * @{
- */
-
-/** @addtogroup STM32H7xx_System_Private_Includes
- * @{
- */
-
-#include "stm32h7xx.h"
-#include <math.h>
-#ifdef __rtems__
-#include <bsp/linker-symbols.h>
-#endif /* __rtems__ */
-#if !defined (HSE_VALUE)
-#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined (CSI_VALUE)
- #define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* CSI_VALUE */
-
-#if !defined (HSI_VALUE)
- #define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-
-/**
- * @}
- */
-
-/** @addtogroup STM32H7xx_System_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32H7xx_System_Private_Defines
- * @{
- */
-
-/************************* Miscellaneous Configuration ************************/
-/*!< Uncomment the following line if you need to use initialized data in D2 domain SRAM (AHB SRAM) */
-/* #define DATA_IN_D2_SRAM */
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
- Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET 0x00000000UL /*!< Vector Table base offset field.
- This value must be a multiple of 0x200. */
-/******************************************************************************/
-
-/**
- * @}
- */
-
-/** @addtogroup STM32H7xx_System_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32H7xx_System_Private_Variables
- * @{
- */
- /* This variable is updated in three ways:
- 1) by calling CMSIS function SystemCoreClockUpdate()
- 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
- 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
- Note: If you use this function to configure the system clock; then there
- is no need to call the 2 first functions listed above, since SystemCoreClock
- variable is updated automatically.
- */
-#ifndef __rtems__
- uint32_t SystemCoreClock = 64000000;
- uint32_t SystemD2Clock = 64000000;
-#else /* __rtems__ */
- RTEMS_SECTION(".rtemsstack") uint32_t SystemCoreClock;
- RTEMS_SECTION(".rtemsstack") uint32_t SystemD2Clock;
-#endif /* __rtems__ */
- const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
-
-/**
- * @}
- */
-
-/** @addtogroup STM32H7xx_System_Private_FunctionPrototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32H7xx_System_Private_Functions
- * @{
- */
-
-/**
- * @brief Setup the microcontroller system
- * Initialize the FPU setting and vector table location
- * configuration.
- * @param None
- * @retval None
- */
-void SystemInit (void)
-{
-#if defined (DATA_IN_D2_SRAM)
- __IO uint32_t tmpreg;
-#endif /* DATA_IN_D2_SRAM */
-
- /* FPU settings ------------------------------------------------------------*/
- #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */
- #endif
- /* Reset the RCC clock configuration to the default reset state ------------*/
- /* Set HSION bit */
- RCC->CR |= RCC_CR_HSION;
-
- /* Reset CFGR register */
- RCC->CFGR = 0x00000000;
-
- /* Reset HSEON, CSSON , CSION,RC48ON, CSIKERON PLL1ON, PLL2ON and PLL3ON bits */
- RCC->CR &= 0xEAF6ED7FU;
-
-#if defined(D3_SRAM_BASE)
- /* Reset D1CFGR register */
- RCC->D1CFGR = 0x00000000;
-
- /* Reset D2CFGR register */
- RCC->D2CFGR = 0x00000000;
-
- /* Reset D3CFGR register */
- RCC->D3CFGR = 0x00000000;
-#else
- /* Reset CDCFGR1 register */
- RCC->CDCFGR1 = 0x00000000;
-
- /* Reset CDCFGR2 register */
- RCC->CDCFGR2 = 0x00000000;
-
- /* Reset SRDCFGR register */
- RCC->SRDCFGR = 0x00000000;
-#endif
- /* Reset PLLCKSELR register */
- RCC->PLLCKSELR = 0x00000000;
-
- /* Reset PLLCFGR register */
- RCC->PLLCFGR = 0x00000000;
- /* Reset PLL1DIVR register */
- RCC->PLL1DIVR = 0x00000000;
- /* Reset PLL1FRACR register */
- RCC->PLL1FRACR = 0x00000000;
-
- /* Reset PLL2DIVR register */
- RCC->PLL2DIVR = 0x00000000;
-
- /* Reset PLL2FRACR register */
-
- RCC->PLL2FRACR = 0x00000000;
- /* Reset PLL3DIVR register */
- RCC->PLL3DIVR = 0x00000000;
-
- /* Reset PLL3FRACR register */
- RCC->PLL3FRACR = 0x00000000;
-
- /* Reset HSEBYP bit */
- RCC->CR &= 0xFFFBFFFFU;
-
- /* Disable all interrupts */
- RCC->CIER = 0x00000000;
-
-#if (STM32H7_DEV_ID == 0x450UL)
- /* dual core CM7 or single core line */
- if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
- {
- /* if stm32h7 revY*/
- /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
- *((__IO uint32_t*)0x51008108) = 0x000000001U;
- }
-#endif
-
-#ifndef __rtems__
-#if defined (DATA_IN_D2_SRAM)
- /* in case of initialized data in D2 SRAM (AHB SRAM) , enable the D2 SRAM clock (AHB SRAM clock) */
-#if defined(RCC_AHB2ENR_D2SRAM3EN)
- RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN);
-#elif defined(RCC_AHB2ENR_D2SRAM2EN)
- RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN);
-#else
- RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN);
-#endif /* RCC_AHB2ENR_D2SRAM3EN */
-
- tmpreg = RCC->AHB2ENR;
- (void) tmpreg;
-#endif /* DATA_IN_D2_SRAM */
-#else /* __rtems__ */
- RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN);
- RCC->AHB2ENR;
-#endif /* __rtems__ */
-
-#ifndef __rtems__
-#if defined(DUAL_CORE) && defined(CORE_CM4)
- /* Configure the Vector Table location add offset address for cortex-M4 ------------------*/
-#ifdef VECT_TAB_SRAM
- SCB->VTOR = D2_AHBSRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
- SCB->VTOR = FLASH_BANK2_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-#endif /* VECT_TAB_SRAM */
-
-#else
-
- /* Configure the Vector Table location add offset address for cortex-M7 ------------------*/
-#ifdef VECT_TAB_SRAM
- SCB->VTOR = D1_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal AXI-RAM */
-#else
- SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-#endif
-
-#endif /*DUAL_CORE && CORE_CM4*/
-#else /* __rtems__ */
- SCB->VTOR = (uint32_t) bsp_start_vector_table_begin;
-#endif /* __rtems__ */
-
-}
-
-/**
- * @brief Update SystemCoreClock variable according to Clock Register Values.
- * The SystemCoreClock variable contains the core clock , it can
- * be used by the user application to setup the SysTick timer or configure
- * other parameters.
- *
- * @note Each time the core clock changes, this function must be called
- * to update SystemCoreClock variable value. Otherwise, any configuration
- * based on this variable will be incorrect.
- *
- * @note - The system frequency computed by this function is not the real
- * frequency in the chip. It is calculated based on the predefined
- * constant and the selected clock source:
- *
- * - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*)
- * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
- * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
- * - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*),
- * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
- *
- * (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
- * 4 MHz) but the real value may vary depending on the variations
- * in voltage and temperature.
- * (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
- * 64 MHz) but the real value may vary depending on the variations
- * in voltage and temperature.
- *
- * (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value
- * 25 MHz), user has to ensure that HSE_VALUE is same as the real
- * frequency of the crystal used. Otherwise, this function may
- * have wrong result.
- *
- * - The result of this function could be not correct when using fractional
- * value for HSE crystal.
- * @param None
- * @retval None
- */
-void SystemCoreClockUpdate (void)
-{
- uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
- uint32_t common_system_clock;
- float_t fracn1, pllvco;
-
-
- /* Get SYSCLK source -------------------------------------------------------*/
-
- switch (RCC->CFGR & RCC_CFGR_SWS)
- {
- case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
- common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
- break;
-
- case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */
- common_system_clock = CSI_VALUE;
- break;
-
- case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
- common_system_clock = HSE_VALUE;
- break;
-
- case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */
-
- /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
- SYSCLK = PLL_VCO / PLLR
- */
- pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
- pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ;
- pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos);
- fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
-
- if (pllm != 0U)
- {
- switch (pllsource)
- {
- case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */
-
- hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
- pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
-
- break;
-
- case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */
- pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
- break;
-
- case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */
- pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
- break;
-
- default:
- pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
- break;
- }
- pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;
- common_system_clock = (uint32_t)(float_t)(pllvco/(float_t)pllp);
- }
- else
- {
- common_system_clock = 0U;
- }
- break;
-
- default:
- common_system_clock = CSI_VALUE;
- break;
- }
-
- /* Compute SystemClock frequency --------------------------------------------------*/
-#if defined (RCC_D1CFGR_D1CPRE)
- tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos];
-
- /* common_system_clock frequency : CM7 CPU frequency */
- common_system_clock >>= tmp;
-
- /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */
- SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
-
-#else
- tmp = D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos];
-
- /* common_system_clock frequency : CM7 CPU frequency */
- common_system_clock >>= tmp;
-
- /* SystemD2Clock frequency : AXI and AHBs Clock frequency */
- SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
-
-#endif
-
-#if defined(DUAL_CORE) && defined(CORE_CM4)
- SystemCoreClock = SystemD2Clock;
-#else
- SystemCoreClock = common_system_clock;
-#endif /* DUAL_CORE && CORE_CM4 */
-}
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--
2.25.1
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