bsp/riscv: Store/AMO address misaligned trap occured

[Padmarao.Begari at microchip.com]

Hi Sebastian,

The "Store/AMO address misaligned" trap occured in the "start.S"
 at "amoswap.w zero, zero, 0(t0)" while testing the sample
 application with the latest RTEMS master for RISC-V on
the Microchip PolarFire SoC.

The trap occured after this  89ba2a98/rtems<https://devel.rtems.org/changeset/89ba2a9838558841c4f38283e84b99173790d61c/rtems> latest commit for riscv
(bsps/riscv: Workaround for sporadic linker issues).

Regards
Padmarao
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