[PATCH] riscv: Simplify _CPU_ISR_Set_level()

[Sebastian Huber]

Where CPU_ENABLE_ROBUST_THREAD_DISPATCH == TRUE, the only supported interrupt
level allowed to set is 0 (interrupts enabled).  This constraint is enforced by
the API level functions which return an error status for other interrupt
levels.
---
 .../score/cpu/riscv/include/rtems/score/cpu.h | 28 +++++++++----------
 1 file changed, 13 insertions(+), 15 deletions(-)

diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h
index 88f7e7960c..f74ce99684 100644
--- a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h
@@ -193,21 +193,19 @@ static inline bool _CPU_ISR_Is_enabled( unsigned long level )
 
 static inline void _CPU_ISR_Set_level( uint32_t level )
 {
-  if ( ( level & CPU_MODES_INTERRUPT_MASK) == 0 ) {
-    __asm__ volatile (
-      ".option push\n"
-      ".option arch, +zicsr\n"
-      "csrrs zero, mstatus, " RTEMS_XSTRING( RISCV_MSTATUS_MIE ) "\n"
-      ".option pop"
-    );
-  } else {
-    __asm__ volatile (
-      ".option push\n"
-      ".option arch, +zicsr\n"
-      "csrrc zero, mstatus, " RTEMS_XSTRING( RISCV_MSTATUS_MIE ) "\n"
-      ".option pop"
-    );
-  }
+  /*
+   * Where CPU_ENABLE_ROBUST_THREAD_DISPATCH == TRUE, the only supported
+   * interrupt level allowed to set is 0 (interrupts enabled).  This constraint
+   * is enforced by the API level functions which return an error status for
+   * other interrupt levels.
+   */
+  (void) level;
+  __asm__ volatile (
+    ".option push\n"
+    ".option arch, +zicsr\n"
+    "csrrs zero, mstatus, " RTEMS_XSTRING( RISCV_MSTATUS_MIE ) "\n"
+    ".option pop"
+  );
 }
 
 uint32_t _CPU_ISR_Get_level( void );
-- 
2.35.3