[PATCH 01/10] bsps/riscv: bsp_interrupt_is_valid_vector()

[Sebastian Huber]

Implement this function.
---
 bsps/riscv/riscv/include/bsp/irq.h |  2 ++
 bsps/riscv/riscv/irq/irq.c         | 17 ++++++++++++++++-
 2 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/bsps/riscv/riscv/include/bsp/irq.h b/bsps/riscv/riscv/include/bsp/irq.h
index ae1ba3c757..93c9780111 100644
--- a/bsps/riscv/riscv/include/bsp/irq.h
+++ b/bsps/riscv/riscv/include/bsp/irq.h
@@ -58,6 +58,8 @@
 
 #define BSP_INTERRUPT_VECTOR_COUNT RISCV_INTERRUPT_VECTOR_EXTERNAL(RISCV_MAXIMUM_EXTERNAL_INTERRUPTS)
 
+#define BSP_INTERRUPT_CUSTOM_VALID_VECTOR
+
 rtems_status_code bsp_interrupt_set_affinity(
   rtems_vector_number vector,
   const Processor_mask *affinity
diff --git a/bsps/riscv/riscv/irq/irq.c b/bsps/riscv/riscv/irq/irq.c
index 1f383ebb89..943dd4a68b 100644
--- a/bsps/riscv/riscv/irq/irq.c
+++ b/bsps/riscv/riscv/irq/irq.c
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
 /**
  * @file
  *
@@ -7,7 +9,7 @@
  */
 
 /*
- * Copyright (c) 2018 embedded brains GmbH
+ * Copyright (C) 2018, 2022 embedded brains GmbH
  *
  * Copyright (c) 2015 University of York.
  * Hesham Almatary <hesham at alumni.york.ac.uk>
@@ -274,6 +276,19 @@ void bsp_interrupt_facility_initialize(void)
   riscv_plic_init(fdt);
 }
 
+bool bsp_interrupt_is_valid_vector(rtems_vector_number vector)
+{
+  /*
+   * The PLIC interrupt ID of zero is reserved.  For example, this ID is used
+   * to indicate that no interrupt was claimed.
+   */
+  if (vector == RISCV_INTERRUPT_VECTOR_EXTERNAL(0)) {
+    return false;
+  }
+
+  return vector < (rtems_vector_number) BSP_INTERRUPT_VECTOR_COUNT;
+}
+
 rtems_status_code bsp_interrupt_get_attributes(
   rtems_vector_number         vector,
   rtems_interrupt_attributes *attributes
-- 
2.35.3