bsps/riscv: interrupt number mismatch

[Padmarao.Begari at microchip.com]

> On Mon, 2022-11-21 at 11:20 +0100, Sebastian Huber wrote:
> 
> On 21/11/2022 11:17, Padmarao.Begari at microchip.com wrote:
> > > To which number would you map the software and timer interrupts?
> > > 
> > The Software and Timer interrupts(numbers 0 & 1) are mapped by
> > the Machine cause register (mcause) and enabled by the CLINT but
> > not by
> > the PLIC.
> 
> Yes, this is the problem. We need an interrupt vector number for all
> interrupts (PLIC and CLINT).
> 

Fixed, by adding 2 with interrupt number in the bsp_fdt_map_intr()
function.
----------------------------------------------------------------
uint32_t bsp_fdt_map_intr(const uint32_t *intr, size_t icells)
{
  (void) icells;
  return intr[0] + 2;
}
----------------------------------------------------------------

Regards
Padmarao 
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