bsps/riscv: interrupt number mismatch

[Sebastian Huber]

On 21/11/2022 11:17, Padmarao.Begari at microchip.com wrote:
>> To which number would you map the software and timer interrupts?
>>
> The Software and Timer interrupts(numbers 0 & 1) are mapped by
> the Machine cause register (mcause) and enabled by the CLINT but not by
> the PLIC.

Yes, this is the problem. We need an interrupt vector number for all 
interrupts (PLIC and CLINT).

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