[PATCH v2 06/13] score: Add CPU_THREAD_LOCAL_STORAGE_VARIANT

[Chris Johns]

On 7/10/2022 3:33 pm, Sebastian Huber wrote:
> On 07.10.22 06:31, Chris Johns wrote:
>> On 7/10/2022 3:23 pm, Sebastian Huber wrote:
>>> On 07.10.22 05:44, Chris Johns wrote:
>>>> On 6/10/2022 7:23 pm, Sebastian Huber wrote:
>>>>> +#if CPU_THREAD_LOCAL_STORAGE_VARIANT == 10
>>>>> +  tls_data = (void *)
>>>>> +    RTEMS_ALIGN_UP( (uintptr_t) tls_area + sizeof( *tcb ), alignment );
>>>>> +  tcb = (TLS_Thread_control_block *) ((char *) tls_data - sizeof( *tcb ));
>>>>> +  return_value = tls_data;
>>>>> +#elif CPU_THREAD_LOCAL_STORAGE_VARIANT == 11
>>>>> +  tcb_size = RTEMS_ALIGN_UP( sizeof( *tcb ), alignment );
>>>>> +  tls_data = (void *)
>>>>> +    RTEMS_ALIGN_UP( (uintptr_t) tls_area + tcb_size, alignment );
>>>>> +  tcb = (TLS_Thread_control_block *) ((char *) tls_data - tcb_size);
>>>>> +  return_value = tcb;
>>>>> +#elif CPU_THREAD_LOCAL_STORAGE_VARIANT == 20
>>>>> +  alignment_2 = RTEMS_ALIGN_UP( alignment, CPU_SIZEOF_POINTER );
>>>>> +  tls_area = (void *) RTEMS_ALIGN_UP( (uintptr_t) tls_area, alignment_2 );
>>>>> +  size = _TLS_Get_size();
>>>>> +  tcb = (TLS_Thread_control_block *)
>>>>> +    ((char *) tls_area + RTEMS_ALIGN_UP( size, alignment_2 ));
>>>>> +  tls_data = (char *) tcb - RTEMS_ALIGN_UP( size, alignment );
>>>>> +  return_value = tcb;
>>>>> +#else
>>>>> +#error "unexpected CPU_THREAD_LOCAL_STORAGE_VARIANT value"
>>>> What are the expected values? I can see 10, 11, 20.
>>>>
>>>> Can this please be changed to something readable? For example:
>>>>
>>>> #if CPU_THREAD_LOCAL_STORAGE_VARIANT == CPU_THREAD_LOCAL_STORAGE_BLAH
>>>>
>>>> #elif CPU_THREAD_LOCAL_STORAGE_VARIANT == CPU_THREAD_LOCAL_STORAGE_BLAH_BLAH
>>>
>>> This is documented in the no_cpu/cpuimpl.h. I think the numbers are all right if
>>> you know the TLS variants. Otherwise we would have to add an extra header file
>>> just for the CPU_THREAD_LOCAL_STORAGE_* defines.
>>
>> Is the doco in this patch? I could not find it.
> 
> Yes, all the CPU port options are documented in the no_cpu port:
> 
> diff --git a/cpukit/score/cpu/no_cpu/include/rtems/score/cpuimpl.h
> b/cpukit/score/cpu/no_cpu/include/rtems/score/cpuimpl.h
> index d5082383e8..72d223de24 100644
> --- a/cpukit/score/cpu/no_cpu/include/rtems/score/cpuimpl.h
> +++ b/cpukit/score/cpu/no_cpu/include/rtems/score/cpuimpl.h
> @@ -54,6 +54,24 @@
>   */
>  #define CPU_PER_CPU_CONTROL_SIZE 0
> 
> +/**
> + * @brief Defines the thread-local storage (TLS) variant.
> + *
> + * Use one of the following values:
> + *
> + * 10: The architecture uses Variant I and the TLS offsets emitted by the
> + *     linker neglect the TCB (examples: nios2, m68k, microblaze, powerpc,
> + *     riscv).  The thread pointer directly references the thread-local data
> + *     area.
> + *
> + * 11: The architecture uses Variant I and the TLS offsets emitted by the
> + *     linker take the TCB into account (examples: arm, aarch64).
> + *     The thread pointer references the TCB.
> + *
> + * 20: The architecture uses Variant II (examples: i386, sparc).
> + */
> +#define CPU_THREAD_LOCAL_STORAGE_VARIANT 10
> +
>  #ifndef ASM
> 
>  #ifdef __cplusplus

Thanks. The number now make sense to me.

Chris