[PATCH 2/3] bsps/riscv: Add Microchip PolarFire SoC BSP variant

Padmarao Begari padmarao.begari at microchip.com
Thu Sep 8 15:43:31 UTC 2022


The Microchip PolarFire SoC support is implemented as a
riscv BSP variant to boot with any individual hart(cpu core)
or SMP based on the boot HARTID configurable and support
components are 4 CPU Cores (U54), Interrupt controller (PLIC),
Timer (CLINT), UART.
---
 bsps/riscv/riscv/clock/clockdrv.c             |  6 +-
 bsps/riscv/riscv/config/mpfs64imafdc.cfg      |  9 ++
 bsps/riscv/riscv/include/bsp/riscv.h          |  4 +
 bsps/riscv/riscv/irq/irq.c                    | 83 ++++++++++++++++++-
 bsps/riscv/riscv/start/bsp_fatal_halt.c       |  3 +
 bsps/riscv/riscv/start/bspsmp.c               |  2 +-
 bsps/riscv/riscv/start/bspstart.c             | 20 ++++-
 bsps/riscv/shared/start/start.S               |  2 +
 .../score/cpu/riscv/include/rtems/score/cpu.h |  2 +-
 .../cpu/riscv/include/rtems/score/cpuimpl.h   |  2 +-
 spec/build/bsps/riscv/optextirqmax.yml        |  5 +-
 spec/build/bsps/riscv/optrambegin.yml         |  5 +-
 spec/build/bsps/riscv/optramsize.yml          |  5 +-
 spec/build/bsps/riscv/riscv/abi.yml           |  6 ++
 .../bsps/riscv/riscv/bspmpfs64imafdc.yml      | 19 +++++
 spec/build/bsps/riscv/riscv/grp.yml           |  6 ++
 spec/build/bsps/riscv/riscv/optdtb.yml        | 19 +++++
 .../bsps/riscv/riscv/optdtbheaderpath.yml     | 20 +++++
 spec/build/bsps/riscv/riscv/optmpfs.yml       | 18 ++++
 spec/build/bsps/riscv/riscv/optns16550max.yml |  3 +
 spec/build/cpukit/cpuopts.yml                 |  2 +
 spec/build/cpukit/optarchbits.yml             |  1 +
 spec/build/cpukit/optboothartid.yml           | 19 +++++
 spec/build/cpukit/optsmp.yml                  |  1 +
 24 files changed, 247 insertions(+), 15 deletions(-)
 create mode 100644 bsps/riscv/riscv/config/mpfs64imafdc.cfg
 create mode 100644 spec/build/bsps/riscv/riscv/bspmpfs64imafdc.yml
 create mode 100644 spec/build/bsps/riscv/riscv/optdtb.yml
 create mode 100644 spec/build/bsps/riscv/riscv/optdtbheaderpath.yml
 create mode 100644 spec/build/bsps/riscv/riscv/optmpfs.yml
 create mode 100644 spec/build/cpukit/optboothartid.yml

diff --git a/bsps/riscv/riscv/clock/clockdrv.c b/bsps/riscv/riscv/clock/clockdrv.c
index 65bc7c80ef..e304ef854b 100644
--- a/bsps/riscv/riscv/clock/clockdrv.c
+++ b/bsps/riscv/riscv/clock/clockdrv.c
@@ -93,7 +93,7 @@ static void riscv_clock_at_tick(riscv_timecounter *tc)
 {
   volatile RISCV_CLINT_regs *clint;
   uint64_t value;
-  uint32_t cpu = rtems_scheduler_get_processor();
+  uint32_t cpu = rtems_scheduler_get_processor() + RTEMS_BOOT_HARTID;
 
   clint = tc->clint;
 
@@ -170,7 +170,7 @@ static void riscv_clock_secondary_action(void *arg)
 {
   volatile RISCV_CLINT_regs *clint = riscv_clint;
   uint64_t *cmpval = arg;
-  uint32_t cpu = _CPU_SMP_Get_current_processor();
+  uint32_t cpu = _CPU_SMP_Get_current_processor() + RTEMS_BOOT_HARTID;
 
   riscv_clock_clint_init(clint, *cmpval, cpu);
 }
@@ -214,7 +214,7 @@ static void riscv_clock_initialize(void)
   cmpval = riscv_clock_read_mtime(&clint->mtime);
   cmpval += interval;
 
-  riscv_clock_clint_init(clint, cmpval, 0);
+  riscv_clock_clint_init(clint, cmpval, RTEMS_BOOT_HARTID);
   riscv_clock_secondary_initialization(clint, cmpval, interval);
 
   /* Initialize timecounter */
diff --git a/bsps/riscv/riscv/config/mpfs64imafdc.cfg b/bsps/riscv/riscv/config/mpfs64imafdc.cfg
new file mode 100644
index 0000000000..b04e78b0e9
--- /dev/null
+++ b/bsps/riscv/riscv/config/mpfs64imafdc.cfg
@@ -0,0 +1,9 @@
+include $(RTEMS_ROOT)/make/custom/default.cfg
+
+RTEMS_CPU = riscv
+
+CPU_CFLAGS = -march=rv64imafdc -mabi=lp64d -mcmodel=medany
+
+LDFLAGS = -Wl,--gc-sections
+
+CFLAGS_OPTIMIZE_V ?= -O2 -g -ffunction-sections -fdata-sections
diff --git a/bsps/riscv/riscv/include/bsp/riscv.h b/bsps/riscv/riscv/include/bsp/riscv.h
index a469155865..d38f46c069 100644
--- a/bsps/riscv/riscv/include/bsp/riscv.h
+++ b/bsps/riscv/riscv/include/bsp/riscv.h
@@ -40,11 +40,15 @@ void *riscv_fdt_get_address(const void *fdt, int node);
 
 uint32_t riscv_get_core_frequency(void);
 
+#if RISCV_ENABLE_MPFS_SUPPORT != 0
+extern uint32_t riscv_hart_count;
+#else
 #ifdef RTEMS_SMP
 extern uint32_t riscv_hart_count;
 #else
 #define riscv_hart_count 1
 #endif
+#endif
 
 uint32_t riscv_get_hart_index_by_phandle(uint32_t phandle);
 
diff --git a/bsps/riscv/riscv/irq/irq.c b/bsps/riscv/riscv/irq/irq.c
index 1b632289a6..4a5697a0bf 100644
--- a/bsps/riscv/riscv/irq/irq.c
+++ b/bsps/riscv/riscv/irq/irq.c
@@ -136,13 +136,25 @@ static void riscv_clint_init(const void *fdt)
     Per_CPU_Control *cpu;
 
     hart_index = riscv_get_hart_index_by_phandle(fdt32_to_cpu(val[i / 4]));
-    if (hart_index >= rtems_configuration_get_maximum_processors()) {
+#ifdef RTEMS_SMP
+    if ((hart_index < RTEMS_BOOT_HARTID) ||
+        (hart_index >= (rtems_configuration_get_maximum_processors() +
+         RTEMS_BOOT_HARTID))) {
+      continue;
+    }
+
+    cpu = _Per_CPU_Get_by_index(hart_index - RTEMS_BOOT_HARTID);
+    cpu->cpu_per_cpu.clint_msip = &clint->msip[i / 16];
+    cpu->cpu_per_cpu.clint_mtimecmp = &clint->mtimecmp[i / 16];
+#else
+    if (hart_index != RTEMS_BOOT_HARTID) {
       continue;
     }
 
-    cpu = _Per_CPU_Get_by_index(hart_index);
+    cpu = _Per_CPU_Get_by_index(0);
     cpu->cpu_per_cpu.clint_msip = &clint->msip[i / 16];
     cpu->cpu_per_cpu.clint_mtimecmp = &clint->mtimecmp[i / 16];
+#endif
   }
 }
 
@@ -183,9 +195,19 @@ static void riscv_plic_init(const void *fdt)
 
   for (i = 0; i < len; i += 8) {
     uint32_t hart_index;
+    uint8_t mie_regs;
+
+    /*
+     * Interrupt enable  registers with 32-bit alignment based on
+     * number of interrupts.
+     */
+    mie_regs =  (ndev + 0x1f) & ~(0x1f);
 
     hart_index = riscv_get_hart_index_by_phandle(fdt32_to_cpu(val[i / 4]));
-    if (hart_index >= rtems_configuration_get_maximum_processors()) {
+#ifdef RTEMS_SMP
+    if ((hart_index < RTEMS_BOOT_HARTID) ||
+        (hart_index >= (rtems_configuration_get_maximum_processors() +
+         RTEMS_BOOT_HARTID))) {
       continue;
     }
 
@@ -196,9 +218,31 @@ static void riscv_plic_init(const void *fdt)
 
     plic->harts[i / 8].priority_threshold = 0;
 
-    cpu = _Per_CPU_Get_by_index(hart_index);
+    cpu = _Per_CPU_Get_by_index(hart_index - RTEMS_BOOT_HARTID);
+    cpu->cpu_per_cpu.plic_hart_regs = &plic->harts[i / 8];
+    cpu->cpu_per_cpu.plic_m_ie = &plic->enable[i / 8][0];
+
+    for (interrupt_index = 0; interrupt_index < mie_regs; ++interrupt_index) {
+        cpu->cpu_per_cpu.plic_m_ie[interrupt_index] = 0;
+    }
+#else
+    if (hart_index != RTEMS_BOOT_HARTID) {
+      continue;
+    }
+
+    interrupt_index = fdt32_to_cpu(val[i / 4 + 1]);
+    if (interrupt_index != RISCV_INTERRUPT_EXTERNAL_MACHINE) {
+      continue;
+    }
+    plic->harts[i / 8].priority_threshold = 0;
+
+    cpu = _Per_CPU_Get_by_index(0);
     cpu->cpu_per_cpu.plic_hart_regs = &plic->harts[i / 8];
     cpu->cpu_per_cpu.plic_m_ie = &plic->enable[i / 8][0];
+    for (interrupt_index = 0; interrupt_index < mie_regs; ++interrupt_index) {
+        cpu->cpu_per_cpu.plic_m_ie[interrupt_index] = 0;
+    }
+#endif
   }
 
   cpu = _Per_CPU_Get_by_index(0);
@@ -298,6 +342,7 @@ rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector)
     if (enable != NULL) {
       enable[group] |= bit;
     } else {
+#ifdef RTEMS_SMP
       uint32_t cpu_max;
       uint32_t cpu_index;
 
@@ -313,6 +358,16 @@ rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector)
           enable[group] |= bit;
         }
       }
+#else
+      Per_CPU_Control *cpu;
+
+      cpu = _Per_CPU_Get_by_index(0);
+      enable = cpu->cpu_per_cpu.plic_m_ie;
+
+      if (enable != NULL) {
+        enable[group] |= bit;
+      }
+#endif
     }
 
     rtems_interrupt_lock_release(&riscv_plic_lock, &lock_context);
@@ -342,6 +397,7 @@ rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector)
     if (enable != NULL) {
       enable[group] &= ~bit;
     } else {
+#ifdef RTEMS_SMP
       uint32_t cpu_max;
       uint32_t cpu_index;
 
@@ -357,6 +413,16 @@ rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector)
           enable[group] &= ~bit;
         }
       }
+#else
+      Per_CPU_Control *cpu;
+
+      cpu = _Per_CPU_Get_by_index(0);
+      enable = cpu->cpu_per_cpu.plic_m_ie;
+
+      if (enable != NULL) {
+        enable[group] &= ~bit;
+      }
+#endif
     }
 
     rtems_interrupt_lock_release(&riscv_plic_lock, &lock_context);
@@ -414,6 +480,7 @@ rtems_status_code bsp_interrupt_get_affinity(
     enable = riscv_plic_irq_to_cpu[interrupt_index - 1];
 
     if (enable != NULL) {
+#ifdef RTEMS_SMP
       uint32_t cpu_max;
       uint32_t cpu_index;
 
@@ -429,6 +496,14 @@ rtems_status_code bsp_interrupt_get_affinity(
           break;
         }
       }
+#else
+      Per_CPU_Control *cpu;
+
+      cpu = _Per_CPU_Get_by_index(0);
+
+      if (enable == cpu->cpu_per_cpu.plic_m_ie)
+        _Processor_mask_Set(affinity, 0);
+#endif
     } else {
       _Processor_mask_Assign(affinity, _SMP_Get_online_processors());
     }
diff --git a/bsps/riscv/riscv/start/bsp_fatal_halt.c b/bsps/riscv/riscv/start/bsp_fatal_halt.c
index d9708661a7..fb0787c606 100644
--- a/bsps/riscv/riscv/start/bsp_fatal_halt.c
+++ b/bsps/riscv/riscv/start/bsp_fatal_halt.c
@@ -41,6 +41,9 @@ void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error )
 #if RISCV_ENABLE_HTIF_SUPPORT != 0
   htif_poweroff();
 #endif
+#if RISCV_ENABLE_MPFS_SUPPORT != 0
+  for(;;);
+#endif
 
   fdt = bsp_fdt_get();
   node = fdt_node_offset_by_compatible(fdt, -1, "sifive,test0");
diff --git a/bsps/riscv/riscv/start/bspsmp.c b/bsps/riscv/riscv/start/bspsmp.c
index 4f1b3c93cc..153a7727e4 100644
--- a/bsps/riscv/riscv/start/bspsmp.c
+++ b/bsps/riscv/riscv/start/bspsmp.c
@@ -49,7 +49,7 @@ void bsp_start_on_secondary_processor(Per_CPU_Control *cpu_self)
 
 uint32_t _CPU_SMP_Initialize(void)
 {
-  return riscv_hart_count;
+  return riscv_hart_count - RTEMS_BOOT_HARTID;
 }
 
 bool _CPU_SMP_Start_processor(uint32_t cpu_index)
diff --git a/bsps/riscv/riscv/start/bspstart.c b/bsps/riscv/riscv/start/bspstart.c
index d33e9965f8..fa600926dd 100644
--- a/bsps/riscv/riscv/start/bspstart.c
+++ b/bsps/riscv/riscv/start/bspstart.c
@@ -74,6 +74,10 @@ void *riscv_fdt_get_address(const void *fdt, int node)
   return (void *)(uintptr_t) addr;
 }
 
+#if RISCV_ENABLE_MPFS_SUPPORT != 0
+uint32_t riscv_hart_count;
+static uint32_t riscv_hart_phandles[5];
+#else
 #ifdef RTEMS_SMP
 uint32_t riscv_hart_count;
 
@@ -81,6 +85,7 @@ static uint32_t riscv_hart_phandles[CPU_MAXIMUM_PROCESSORS];
 #else
 static uint32_t riscv_hart_phandles[1];
 #endif
+#endif
 
 static void riscv_find_harts(void)
 {
@@ -146,9 +151,13 @@ static void riscv_find_harts(void)
     riscv_hart_phandles[hart_index] = phandle;
   }
 
+#if RISCV_ENABLE_MPFS_SUPPORT != 0
+  riscv_hart_count = max_hart_index + 1;
+#else
 #ifdef RTEMS_SMP
   riscv_hart_count = max_hart_index + 1;
 #endif
+#endif
 }
 
 uint32_t riscv_get_hart_index_by_phandle(uint32_t phandle)
@@ -166,7 +175,7 @@ uint32_t riscv_get_hart_index_by_phandle(uint32_t phandle)
 
 static uint32_t get_core_frequency(void)
 {
-#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0
+#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0 || RISCV_ENABLE_MPFS_SUPPORT != 0
   uint32_t node;
   const char *fdt;
   const char *tlclk;
@@ -177,7 +186,14 @@ static uint32_t get_core_frequency(void)
   node = fdt_node_offset_by_compatible(fdt, -1,"fixed-clock");
   tlclk = fdt_getprop(fdt, node, "clock-output-names", &len);
 
-  if (strcmp(tlclk,"tlclk") != 0) {
+#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0
+  if (strcmp(tlclk,"tlclk") != 0)
+#endif
+#if RISCV_ENABLE_MPFS_SUPPORT != 0
+  if (strcmp(tlclk,"msspllclk") != 0)
+#endif
+  {
+
     bsp_fatal(RISCV_FATAL_NO_TLCLOCK_FREQUENCY_IN_DEVICE_TREE);
   }
 
diff --git a/bsps/riscv/shared/start/start.S b/bsps/riscv/shared/start/start.S
index 3702f8ac2f..3d27098d11 100644
--- a/bsps/riscv/shared/start/start.S
+++ b/bsps/riscv/shared/start/start.S
@@ -65,6 +65,8 @@ SYM(_start):
 	LADDR	sp, _ISR_Stack_area_begin
 	LADDR	t2, _ISR_Stack_size
 	csrr	s0, mhartid
+	li      t3, RTEMS_BOOT_HARTID
+	sub     s0, s0, t3
 	LADDR	t0, _Per_CPU_Information
 	slli	t1, s0, PER_CPU_CONTROL_SIZE_LOG2
 	add	s1, t0, t1
diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h
index 471c6c6c3e..ba1cad8b58 100644
--- a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h
@@ -489,7 +489,7 @@ static inline uint32_t _CPU_SMP_Get_current_processor( void )
     "=&r" ( mhartid )
   );
 
-  return (uint32_t) mhartid;
+  return (uint32_t) mhartid - RTEMS_BOOT_HARTID;
 }
 
 void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h
index ca09832d0e..f95d65b123 100644
--- a/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h
@@ -325,7 +325,7 @@ typedef struct {
   uint32_t priority[RISCV_PLIC_MAX_INTERRUPTS];
   uint32_t pending[1024];
   uint32_t enable[16320][32];
-  RISCV_PLIC_hart_regs harts[CPU_MAXIMUM_PROCESSORS];
+  RISCV_PLIC_hart_regs harts[CPU_MAXIMUM_PROCESSORS + RTEMS_BOOT_HARTID];
 } RISCV_PLIC_regs;
 
 typedef struct {
diff --git a/spec/build/bsps/riscv/optextirqmax.yml b/spec/build/bsps/riscv/optextirqmax.yml
index ffa84748b6..84dbbb7705 100644
--- a/spec/build/bsps/riscv/optextirqmax.yml
+++ b/spec/build/bsps/riscv/optextirqmax.yml
@@ -6,7 +6,10 @@ build-type: option
 copyrights:
 - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
 default: 64
-default-by-variant: []
+default-by-variant:
+- value: 187
+  variants:
+  - riscv/mpfs64.*
 description: |
   maximum number of external interrupts supported by the BSP (default 64)
 enabled-by: true
diff --git a/spec/build/bsps/riscv/optrambegin.yml b/spec/build/bsps/riscv/optrambegin.yml
index 4a867a1921..90133411cf 100644
--- a/spec/build/bsps/riscv/optrambegin.yml
+++ b/spec/build/bsps/riscv/optrambegin.yml
@@ -1,7 +1,7 @@
 SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
 actions:
 - get-integer: null
-- assert-uint32: null
+- assert-uint64: null
 - assert-aligned: 1048576
 - env-assign: null
 - format-and-define: null
@@ -22,6 +22,9 @@ default-by-variant:
 - value: 1073741824
   variants:
   - riscv/griscv
+- value: 68719476736
+  variants:
+  - riscv/mpfs64.*
 description: ''
 enabled-by: true
 format: '{:#010x}'
diff --git a/spec/build/bsps/riscv/optramsize.yml b/spec/build/bsps/riscv/optramsize.yml
index cd58dbd504..316cc906de 100644
--- a/spec/build/bsps/riscv/optramsize.yml
+++ b/spec/build/bsps/riscv/optramsize.yml
@@ -1,7 +1,7 @@
 SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
 actions:
 - get-integer: null
-- assert-uint32: null
+- assert-uint64: null
 - assert-aligned: 1048576
 - env-assign: null
 - format-and-define: null
@@ -16,6 +16,9 @@ default-by-variant:
 - value: 16777216
   variants:
   - riscv/griscv
+- value: 268435456
+  variants:
+  - riscv/mpfs64.*
 description: ''
 enabled-by: true
 format: '{:#010x}'
diff --git a/spec/build/bsps/riscv/riscv/abi.yml b/spec/build/bsps/riscv/riscv/abi.yml
index e975b87c4c..3ef8b0681d 100644
--- a/spec/build/bsps/riscv/riscv/abi.yml
+++ b/spec/build/bsps/riscv/riscv/abi.yml
@@ -10,6 +10,12 @@ default:
 - -march=rv32imac
 - -mabi=ilp32
 default-by-variant:
+- value:
+  - -march=rv64imafdc
+  - -mabi=lp64d
+  - -mcmodel=medany
+  variants:
+  - riscv/mpfs64imafdc
 - value:
   - -march=rv64imafdc
   - -mabi=lp64d
diff --git a/spec/build/bsps/riscv/riscv/bspmpfs64imafdc.yml b/spec/build/bsps/riscv/riscv/bspmpfs64imafdc.yml
new file mode 100644
index 0000000000..aaef421e14
--- /dev/null
+++ b/spec/build/bsps/riscv/riscv/bspmpfs64imafdc.yml
@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+arch: riscv
+bsp: mpfs64imafdc
+build-type: bsp
+cflags: []
+copyrights:
+- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+cppflags: []
+enabled-by: true
+family: riscv
+includes: []
+install: []
+links:
+- role: build-dependency
+  uid: ../../opto0
+- role: build-dependency
+  uid: grp
+source: []
+type: build
diff --git a/spec/build/bsps/riscv/riscv/grp.yml b/spec/build/bsps/riscv/riscv/grp.yml
index 7f773d91ee..bd44dedcb2 100644
--- a/spec/build/bsps/riscv/riscv/grp.yml
+++ b/spec/build/bsps/riscv/riscv/grp.yml
@@ -44,10 +44,16 @@ links:
   uid: ../../optfdtro
 - role: build-dependency
   uid: ../../optfdtuboot
+- role: build-dependency
+  uid: optdtb
+- role: build-dependency
+  uid: optdtbheaderpath
 - role: build-dependency
   uid: optfrdme310arty
 - role: build-dependency
   uid: opthtif
+- role: build-dependency
+  uid: optmpfs
 - role: build-dependency
   uid: optns16550max
 - role: build-dependency
diff --git a/spec/build/bsps/riscv/riscv/optdtb.yml b/spec/build/bsps/riscv/riscv/optdtb.yml
new file mode 100644
index 0000000000..54ae7aa770
--- /dev/null
+++ b/spec/build/bsps/riscv/riscv/optdtb.yml
@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-boolean: null
+- define-condition: null
+build-type: option
+copyrights:
+- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+default: false
+default-by-variant:
+- value: true
+  variants:
+  - riscv/mpfs64.*
+description: |
+  the path to the header file containing the device tree binary. See the BSP
+  documentation for more information.
+enabled-by: true
+links: []
+name: BSP_DTB_IS_SUPPORTED
+type: build
diff --git a/spec/build/bsps/riscv/riscv/optdtbheaderpath.yml b/spec/build/bsps/riscv/riscv/optdtbheaderpath.yml
new file mode 100644
index 0000000000..85568b2086
--- /dev/null
+++ b/spec/build/bsps/riscv/riscv/optdtbheaderpath.yml
@@ -0,0 +1,20 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-string: null
+- define: null
+build-type: option
+copyrights:
+- Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
+default: false
+default-by-variant:
+- value: bsp/mpfs_dtb.h
+  variants:
+  - riscv/mpfs64.*
+description: |
+  the path to the header file containing the device tree binary. See the BSP
+  documentation for more information.
+enabled-by: true
+format: '{}'
+links: []
+name: BSP_DTB_HEADER_PATH
+type: build
diff --git a/spec/build/bsps/riscv/riscv/optmpfs.yml b/spec/build/bsps/riscv/riscv/optmpfs.yml
new file mode 100644
index 0000000000..17614567e3
--- /dev/null
+++ b/spec/build/bsps/riscv/riscv/optmpfs.yml
@@ -0,0 +1,18 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-boolean: null
+- define-condition: null
+build-type: option
+copyrights:
+- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+default: false
+default-by-variant:
+- value: true
+  variants:
+  - riscv/mpfs64.*
+description: |
+  enables support Microchip PolarFire SoC if defined to a non-zero value,otherwise it is disabled (disabled by default)
+enabled-by: true
+links: []
+name: RISCV_ENABLE_MPFS_SUPPORT
+type: build
diff --git a/spec/build/bsps/riscv/riscv/optns16550max.yml b/spec/build/bsps/riscv/riscv/optns16550max.yml
index 7e385a57b7..66189cfdfd 100644
--- a/spec/build/bsps/riscv/riscv/optns16550max.yml
+++ b/spec/build/bsps/riscv/riscv/optns16550max.yml
@@ -10,6 +10,9 @@ default-by-variant:
 - value: null
   variants:
   - riscv/frdme310arty.*
+- value: 1
+  variants:
+  - riscv/mpfs64.*
 description: |
   maximum number of NS16550 devices supported by the console driver (2 by default)
 enabled-by: true
diff --git a/spec/build/cpukit/cpuopts.yml b/spec/build/cpukit/cpuopts.yml
index 86cc7f676a..dcfca62d05 100644
--- a/spec/build/cpukit/cpuopts.yml
+++ b/spec/build/cpukit/cpuopts.yml
@@ -33,6 +33,8 @@ links:
   uid: optinstall
 - role: build-dependency
   uid: optada
+- role: build-dependency
+  uid: optboothartid
 - role: build-dependency
   uid: optbuildlabel
 - role: build-dependency
diff --git a/spec/build/cpukit/optarchbits.yml b/spec/build/cpukit/optarchbits.yml
index f7b652cc60..0ec4a9fe7e 100644
--- a/spec/build/cpukit/optarchbits.yml
+++ b/spec/build/cpukit/optarchbits.yml
@@ -11,6 +11,7 @@ default-by-variant:
 - value:
   - '64'
   variants:
+  - riscv/mpfs64.*
   - riscv/noel64.*
   - riscv/rv64.*
 - value:
diff --git a/spec/build/cpukit/optboothartid.yml b/spec/build/cpukit/optboothartid.yml
new file mode 100644
index 0000000000..dc8511970d
--- /dev/null
+++ b/spec/build/cpukit/optboothartid.yml
@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- define: null
+build-type: option
+copyrights:
+- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+default: 0
+default-by-variant:
+- value: 1
+  variants:
+  - riscv/mpfs64.*
+description: | 
+  boot hartid (processor number) of cpu (default 0)
+enabled-by: true
+format: '{}'
+links: []
+name: RTEMS_BOOT_HARTID
+type: build
diff --git a/spec/build/cpukit/optsmp.yml b/spec/build/cpukit/optsmp.yml
index a9e62bf8b9..b218364194 100644
--- a/spec/build/cpukit/optsmp.yml
+++ b/spec/build/cpukit/optsmp.yml
@@ -31,6 +31,7 @@ enabled-by:
 - riscv/griscv
 - riscv/grv32imac
 - riscv/grv32imafdc
+- riscv/mpfs64imafdc
 - riscv/noel32imafd
 - riscv/noel64imac
 - riscv/noel64imafdc
-- 
2.25.1



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