[PATCH 2/3] bsps/riscv: Add Microchip PolarFire SoC BSP variant

[Sebastian Huber]

On 08/09/2022 17:43, Padmarao Begari wrote:
> +++ b/bsps/riscv/riscv/clock/clockdrv.c
> @@ -93,7 +93,7 @@ static void riscv_clock_at_tick(riscv_timecounter *tc)
>   {
>     volatile RISCV_CLINT_regs *clint;
>     uint64_t value;
> -  uint32_t cpu = rtems_scheduler_get_processor();
> +  uint32_t cpu = rtems_scheduler_get_processor() + RTEMS_BOOT_HARTID;

Defines and functions starting with RTEMS_ or rtems_ should belong to 
the architecture-independent RTEMS API. This is specific to RISC-V, so 
it should be RISCV_BOOT_HARDID. I am not sure if your approach is correct.

The numbers returned by rtems_scheduler_get_processor() (also known as 
_CPU_SMP_Get_current_processor()) should range from 0 to the configured 
(and available) processor count minus one. If your SoC has four 
processors then the valid numbers are 0, 1, 2, and 3. If the HARDIDs of 
your SoC range from 1 to n, then you have to map these HARDID numbers so 
that they start with 0 in _CPU_SMP_Get_current_processor().

Another issue is if you boot from a processor other than 0 (as returned 
by _CPU_SMP_Get_current_processor()).

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