[PATCH 2/3] bsps/riscv: Add Microchip PolarFire SoC BSP variant

[Sebastian Huber]

On 08/09/2022 17:43, Padmarao Begari wrote:
> diff --git a/bsps/riscv/riscv/irq/irq.c b/bsps/riscv/riscv/irq/irq.c
> index 1b632289a6..4a5697a0bf 100644
> --- a/bsps/riscv/riscv/irq/irq.c
> +++ b/bsps/riscv/riscv/irq/irq.c
> @@ -136,13 +136,25 @@ static void riscv_clint_init(const void *fdt)
>       Per_CPU_Control *cpu;
>   
>       hart_index = riscv_get_hart_index_by_phandle(fdt32_to_cpu(val[i / 4]));
> -    if (hart_index >= rtems_configuration_get_maximum_processors()) {
> +#ifdef RTEMS_SMP
> +    if ((hart_index < RTEMS_BOOT_HARTID) ||
> +        (hart_index >= (rtems_configuration_get_maximum_processors() +
> +         RTEMS_BOOT_HARTID))) {
> +      continue;
> +    }
> +
> +    cpu = _Per_CPU_Get_by_index(hart_index - RTEMS_BOOT_HARTID);
> +    cpu->cpu_per_cpu.clint_msip = &clint->msip[i / 16];
> +    cpu->cpu_per_cpu.clint_mtimecmp = &clint->mtimecmp[i / 16];

If necessary (see previous e-mail), then there should be a general

uint32_t _RISCV_Map_hardid_to_cpu_index(uint32_t hardid)

uint32_t _RISCV_Map_cpu_index_to_hardid(uint32_t cpu_index)

functions.

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