[PATCH v2 0/4] Microchip PolarFire SoC support

[Padmarao Begari]

This patch set adds the Microchip PolarFire SoC BSP Variant
support to RISC-V RTEMS.

The PolarFire SoC is the 4x 64-bit RISC-V U54 cores and
a 64-bit RISC-V E51 monitor core SoC from Microchip, more
info available here:
	https://www.microchip.com/en-us/products/fpgas-and-plds/
	system-on-chip-fpgas/polarfire-soc-fpgas#Overview

This new BSP variant is added for the 4x U54 cores not for E51
because the E51 monitor core is resreved for first stage
bootloader (Hart Software Services).

The boot HARTID configurable is implemented for the riscv BSP
to work with individual hart(cpu core) or SMP.

This BSP support components: 4 CPU Cores (U54), Interrupt
controller (PLIC), Timer (CLINT), UART (16550-compatible)
work fine on actual Microchip PolarFire SoC Icicle Kit.

v2:
- Add a license and copyright information in dtb header file
- Use RISCV_BOOT_HARDID instead of RTEMS_BOOT_HARDID
- Add '_RISCV_Map_hardid_to_cpu_index()' and
'_RISCV_Map_cpu_index_to_hardid()' functions
- Change bsp_fdt_get() instead of bsp_fdt_copy() function for dtb
- Move dtb and dtb header configurable build option to the bsps

Padmarao Begari (4):
  bsps/riscv: Add device tree blob
  spec/build/bsps: Add dtb support
  bsps/riscv: Add Microchip PolarFire SoC BSP variant
  bsps/shared/: Use device tree blob

 bsps/riscv/riscv/clock/clockdrv.c             |   6 +-
 bsps/riscv/riscv/config/mpfs64imafdc.cfg      |   9 +
 bsps/riscv/riscv/dts/mpfs.dts                 | 365 +++++++++++
 bsps/riscv/riscv/include/bsp/mpfs-dtb.h       | 602 ++++++++++++++++++
 bsps/riscv/riscv/include/bsp/riscv.h          |  14 +
 bsps/riscv/riscv/irq/irq.c                    |  81 +++
 bsps/riscv/riscv/start/bsp_fatal_halt.c       |   3 +
 bsps/riscv/riscv/start/bspsmp.c               |   2 +-
 bsps/riscv/riscv/start/bspstart.c             |  19 +-
 bsps/riscv/shared/start/start.S               |   2 +
 bsps/shared/start/bsp-fdt.c                   |   8 +
 .../score/cpu/riscv/include/rtems/score/cpu.h |   2 +-
 .../cpu/riscv/include/rtems/score/cpuimpl.h   |   2 +-
 spec/build/bsps/optdtb.yml                    |  19 +
 spec/build/bsps/optdtbheaderpath.yml          |  20 +
 spec/build/bsps/riscv/optextirqmax.yml        |   5 +-
 spec/build/bsps/riscv/optrambegin.yml         |   5 +-
 spec/build/bsps/riscv/optramsize.yml          |   5 +-
 spec/build/bsps/riscv/riscv/abi.yml           |   6 +
 .../bsps/riscv/riscv/bspmpfs64imafdc.yml      |  19 +
 spec/build/bsps/riscv/riscv/grp.yml           |   6 +
 spec/build/bsps/riscv/riscv/optmpfs.yml       |  18 +
 spec/build/bsps/riscv/riscv/optns16550max.yml |   3 +
 spec/build/cpukit/cpuopts.yml                 |   2 +
 spec/build/cpukit/optarchbits.yml             |   1 +
 spec/build/cpukit/optboothartid.yml           |  19 +
 spec/build/cpukit/optsmp.yml                  |   1 +
 27 files changed, 1235 insertions(+), 9 deletions(-)
 create mode 100644 bsps/riscv/riscv/config/mpfs64imafdc.cfg
 create mode 100644 bsps/riscv/riscv/dts/mpfs.dts
 create mode 100644 bsps/riscv/riscv/include/bsp/mpfs-dtb.h
 create mode 100644 spec/build/bsps/optdtb.yml
 create mode 100644 spec/build/bsps/optdtbheaderpath.yml
 create mode 100644 spec/build/bsps/riscv/riscv/bspmpfs64imafdc.yml
 create mode 100644 spec/build/bsps/riscv/riscv/optmpfs.yml
 create mode 100644 spec/build/cpukit/optboothartid.yml

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2.25.1